| tb_regs.h (b04079837b2094f09e145676eec4b9a56ae8a6aa) | tb_regs.h (cf29b9afb121494a7aa12dae6eebf81347e0313b) |
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| 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Thunderbolt driver - Port/Switch config area registers 4 * 5 * Every thunderbolt device consists (logically) of a switch with multiple 6 * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH, 7 * COUNTERS) which are used to configure the device. 8 * --- 12 unchanged lines hidden (view full) --- 21 22/* 23 * TODO: should be 63? But we do not know how to receive frames larger than 256 24 * bytes at the frame level. (header + checksum = 16, 60*4 = 240) 25 */ 26#define TB_MAX_CONFIG_RW_LENGTH 60 27 28enum tb_switch_cap { | 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Thunderbolt driver - Port/Switch config area registers 4 * 5 * Every thunderbolt device consists (logically) of a switch with multiple 6 * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH, 7 * COUNTERS) which are used to configure the device. 8 * --- 12 unchanged lines hidden (view full) --- 21 22/* 23 * TODO: should be 63? But we do not know how to receive frames larger than 256 24 * bytes at the frame level. (header + checksum = 16, 60*4 = 240) 25 */ 26#define TB_MAX_CONFIG_RW_LENGTH 60 27 28enum tb_switch_cap { |
| 29 TB_SWITCH_CAP_TMU = 0x03, |
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| 29 TB_SWITCH_CAP_VSE = 0x05, 30}; 31 32enum tb_switch_vse_cap { 33 TB_VSE_CAP_PLUG_EVENTS = 0x01, /* also EEPROM */ 34 TB_VSE_CAP_TIME2 = 0x03, 35 TB_VSE_CAP_IECS = 0x04, 36 TB_VSE_CAP_LINK_CONTROLLER = 0x06, /* also IECS */ --- 153 unchanged lines hidden (view full) --- 190#define ROUTER_CS_9 0x09 191#define ROUTER_CS_25 0x19 192#define ROUTER_CS_26 0x1a 193#define ROUTER_CS_26_STATUS_MASK GENMASK(29, 24) 194#define ROUTER_CS_26_STATUS_SHIFT 24 195#define ROUTER_CS_26_ONS BIT(30) 196#define ROUTER_CS_26_OV BIT(31) 197 | 30 TB_SWITCH_CAP_VSE = 0x05, 31}; 32 33enum tb_switch_vse_cap { 34 TB_VSE_CAP_PLUG_EVENTS = 0x01, /* also EEPROM */ 35 TB_VSE_CAP_TIME2 = 0x03, 36 TB_VSE_CAP_IECS = 0x04, 37 TB_VSE_CAP_LINK_CONTROLLER = 0x06, /* also IECS */ --- 153 unchanged lines hidden (view full) --- 191#define ROUTER_CS_9 0x09 192#define ROUTER_CS_25 0x19 193#define ROUTER_CS_26 0x1a 194#define ROUTER_CS_26_STATUS_MASK GENMASK(29, 24) 195#define ROUTER_CS_26_STATUS_SHIFT 24 196#define ROUTER_CS_26_ONS BIT(30) 197#define ROUTER_CS_26_OV BIT(31) 198 |
| 199/* Router TMU configuration */ 200#define TMU_RTR_CS_0 0x00 201#define TMU_RTR_CS_0_TD BIT(27) 202#define TMU_RTR_CS_0_UCAP BIT(30) 203#define TMU_RTR_CS_1 0x01 204#define TMU_RTR_CS_1_LOCAL_TIME_NS_MASK GENMASK(31, 16) 205#define TMU_RTR_CS_1_LOCAL_TIME_NS_SHIFT 16 206#define TMU_RTR_CS_2 0x02 207#define TMU_RTR_CS_3 0x03 208#define TMU_RTR_CS_3_LOCAL_TIME_NS_MASK GENMASK(15, 0) 209#define TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK GENMASK(31, 16) 210#define TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT 16 211#define TMU_RTR_CS_22 0x16 212#define TMU_RTR_CS_24 0x18 213 |
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| 198enum tb_port_type { 199 TB_TYPE_INACTIVE = 0x000000, 200 TB_TYPE_PORT = 0x000001, 201 TB_TYPE_NHI = 0x000002, 202 /* TB_TYPE_ETHERNET = 0x020000, lower order bits are not known */ 203 /* TB_TYPE_SATA = 0x080000, lower order bits are not known */ 204 TB_TYPE_DP_HDMI_IN = 0x0e0101, 205 TB_TYPE_DP_HDMI_OUT = 0x0e0102, --- 37 unchanged lines hidden (view full) --- 243#define ADP_CS_4_NFC_BUFFERS_MASK GENMASK(9, 0) 244#define ADP_CS_4_TOTAL_BUFFERS_MASK GENMASK(29, 20) 245#define ADP_CS_4_TOTAL_BUFFERS_SHIFT 20 246#define ADP_CS_4_LCK BIT(31) 247#define ADP_CS_5 0x05 248#define ADP_CS_5_LCA_MASK GENMASK(28, 22) 249#define ADP_CS_5_LCA_SHIFT 22 250 | 214enum tb_port_type { 215 TB_TYPE_INACTIVE = 0x000000, 216 TB_TYPE_PORT = 0x000001, 217 TB_TYPE_NHI = 0x000002, 218 /* TB_TYPE_ETHERNET = 0x020000, lower order bits are not known */ 219 /* TB_TYPE_SATA = 0x080000, lower order bits are not known */ 220 TB_TYPE_DP_HDMI_IN = 0x0e0101, 221 TB_TYPE_DP_HDMI_OUT = 0x0e0102, --- 37 unchanged lines hidden (view full) --- 259#define ADP_CS_4_NFC_BUFFERS_MASK GENMASK(9, 0) 260#define ADP_CS_4_TOTAL_BUFFERS_MASK GENMASK(29, 20) 261#define ADP_CS_4_TOTAL_BUFFERS_SHIFT 20 262#define ADP_CS_4_LCK BIT(31) 263#define ADP_CS_5 0x05 264#define ADP_CS_5_LCA_MASK GENMASK(28, 22) 265#define ADP_CS_5_LCA_SHIFT 22 266 |
| 267/* TMU adapter registers */ 268#define TMU_ADP_CS_3 0x03 269#define TMU_ADP_CS_3_UDM BIT(29) 270 |
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| 251/* Lane adapter registers */ 252#define LANE_ADP_CS_0 0x00 253#define LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK GENMASK(25, 20) 254#define LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT 20 255#define LANE_ADP_CS_1 0x01 256#define LANE_ADP_CS_1_TARGET_WIDTH_MASK GENMASK(9, 4) 257#define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT 4 258#define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE 0x1 --- 108 unchanged lines hidden --- | 271/* Lane adapter registers */ 272#define LANE_ADP_CS_0 0x00 273#define LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK GENMASK(25, 20) 274#define LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT 20 275#define LANE_ADP_CS_1 0x01 276#define LANE_ADP_CS_1_TARGET_WIDTH_MASK GENMASK(9, 4) 277#define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT 4 278#define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE 0x1 --- 108 unchanged lines hidden --- |