tb_regs.h (483c9d8275aff428df433e9d7c718609345500e2) tb_regs.h (43f977bc60b1cfd3c1d220a9a0a06493fbf3985d)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Thunderbolt driver - Port/Switch config area registers
4 *
5 * Every thunderbolt device consists (logically) of a switch with multiple
6 * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH,
7 * COUNTERS) which are used to configure the device.
8 *

--- 433 unchanged lines hidden (view full) ---

442 bool egress_fc:1;
443 bool ingress_shared_buffer:1;
444 bool egress_shared_buffer:1;
445 bool pending:1;
446 u32 unknown3:3; /* set to zero */
447} __packed;
448
449/* TMU Thunderbolt 3 registers */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Thunderbolt driver - Port/Switch config area registers
4 *
5 * Every thunderbolt device consists (logically) of a switch with multiple
6 * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH,
7 * COUNTERS) which are used to configure the device.
8 *

--- 433 unchanged lines hidden (view full) ---

442 bool egress_fc:1;
443 bool ingress_shared_buffer:1;
444 bool egress_shared_buffer:1;
445 bool pending:1;
446 u32 unknown3:3; /* set to zero */
447} __packed;
448
449/* TMU Thunderbolt 3 registers */
450#define TB_TIME_VSEC_3_CS_26 0x1a
451#define TB_TIME_VSEC_3_CS_26_TD BIT(22)
450#define TB_TIME_VSEC_3_CS_9 0x9
451#define TB_TIME_VSEC_3_CS_9_TMU_OBJ_MASK GENMASK(17, 16)
452#define TB_TIME_VSEC_3_CS_26 0x1a
453#define TB_TIME_VSEC_3_CS_26_TD BIT(22)
452
454
455/*
456 * Used for Titan Ridge only. Bits are part of the same register: TMU_ADP_CS_6
457 * (see above) as in USB4 spec, but these specific bits used for Titan Ridge
458 * only and reserved in USB4 spec.
459 */
460#define TMU_ADP_CS_6_DISABLE_TMU_OBJ_MASK GENMASK(3, 2)
461#define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL1 BIT(2)
462#define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL2 BIT(3)
463
464/* Plug Events registers */
465#define TB_PLUG_EVENTS_PCIE_WR_DATA 0x1b
466#define TB_PLUG_EVENTS_PCIE_CMD 0x1c
467#define TB_PLUG_EVENTS_PCIE_CMD_DW_OFFSET_MASK GENMASK(9, 0)
468#define TB_PLUG_EVENTS_PCIE_CMD_BR_SHIFT 10
469#define TB_PLUG_EVENTS_PCIE_CMD_BR_MASK GENMASK(17, 10)
470#define TB_PLUG_EVENTS_PCIE_CMD_RD_WR_MASK BIT(21)
471#define TB_PLUG_EVENTS_PCIE_CMD_WR 0x1
472#define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_SHIFT 22
473#define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_MASK GENMASK(24, 22)
474#define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_VAL 0x2
475#define TB_PLUG_EVENTS_PCIE_CMD_REQ_ACK_MASK BIT(30)
476#define TB_PLUG_EVENTS_PCIE_CMD_TIMEOUT_MASK BIT(31)
477#define TB_PLUG_EVENTS_PCIE_CMD_RD_DATA 0x1d
478
479/* CP Low Power registers */
480#define TB_LOW_PWR_C1_CL1 0x1
481#define TB_LOW_PWR_C1_CL1_OBJ_MASK GENMASK(4, 1)
482#define TB_LOW_PWR_C1_CL2_OBJ_MASK GENMASK(4, 1)
483#define TB_LOW_PWR_C1_PORT_A_MASK GENMASK(2, 1)
484#define TB_LOW_PWR_C0_PORT_B_MASK GENMASK(4, 3)
485#define TB_LOW_PWR_C3_CL1 0x3
486
453/* Common link controller registers */
487/* Common link controller registers */
454#define TB_LC_DESC 0x02
455#define TB_LC_DESC_NLC_MASK GENMASK(3, 0)
456#define TB_LC_DESC_SIZE_SHIFT 8
457#define TB_LC_DESC_SIZE_MASK GENMASK(15, 8)
458#define TB_LC_DESC_PORT_SIZE_SHIFT 16
459#define TB_LC_DESC_PORT_SIZE_MASK GENMASK(27, 16)
460#define TB_LC_FUSE 0x03
461#define TB_LC_SNK_ALLOCATION 0x10
462#define TB_LC_SNK_ALLOCATION_SNK0_MASK GENMASK(3, 0)
463#define TB_LC_SNK_ALLOCATION_SNK0_CM 0x1
464#define TB_LC_SNK_ALLOCATION_SNK1_SHIFT 4
465#define TB_LC_SNK_ALLOCATION_SNK1_MASK GENMASK(7, 4)
466#define TB_LC_SNK_ALLOCATION_SNK1_CM 0x1
467#define TB_LC_POWER 0x740
488#define TB_LC_DESC 0x02
489#define TB_LC_DESC_NLC_MASK GENMASK(3, 0)
490#define TB_LC_DESC_SIZE_SHIFT 8
491#define TB_LC_DESC_SIZE_MASK GENMASK(15, 8)
492#define TB_LC_DESC_PORT_SIZE_SHIFT 16
493#define TB_LC_DESC_PORT_SIZE_MASK GENMASK(27, 16)
494#define TB_LC_FUSE 0x03
495#define TB_LC_SNK_ALLOCATION 0x10
496#define TB_LC_SNK_ALLOCATION_SNK0_MASK GENMASK(3, 0)
497#define TB_LC_SNK_ALLOCATION_SNK0_CM 0x1
498#define TB_LC_SNK_ALLOCATION_SNK1_SHIFT 4
499#define TB_LC_SNK_ALLOCATION_SNK1_MASK GENMASK(7, 4)
500#define TB_LC_SNK_ALLOCATION_SNK1_CM 0x1
501#define TB_LC_POWER 0x740
468
469/* Link controller registers */
502
503/* Link controller registers */
470#define TB_LC_PORT_ATTR 0x8d
471#define TB_LC_PORT_ATTR_BE BIT(12)
504#define TB_LC_PORT_ATTR 0x8d
505#define TB_LC_PORT_ATTR_BE BIT(12)
472
506
473#define TB_LC_SX_CTRL 0x96
474#define TB_LC_SX_CTRL_WOC BIT(1)
475#define TB_LC_SX_CTRL_WOD BIT(2)
476#define TB_LC_SX_CTRL_WODPC BIT(3)
477#define TB_LC_SX_CTRL_WODPD BIT(4)
478#define TB_LC_SX_CTRL_WOU4 BIT(5)
479#define TB_LC_SX_CTRL_WOP BIT(6)
480#define TB_LC_SX_CTRL_L1C BIT(16)
481#define TB_LC_SX_CTRL_L1D BIT(17)
482#define TB_LC_SX_CTRL_L2C BIT(20)
483#define TB_LC_SX_CTRL_L2D BIT(21)
484#define TB_LC_SX_CTRL_SLI BIT(29)
485#define TB_LC_SX_CTRL_UPSTREAM BIT(30)
486#define TB_LC_SX_CTRL_SLP BIT(31)
507#define TB_LC_SX_CTRL 0x96
508#define TB_LC_SX_CTRL_WOC BIT(1)
509#define TB_LC_SX_CTRL_WOD BIT(2)
510#define TB_LC_SX_CTRL_WODPC BIT(3)
511#define TB_LC_SX_CTRL_WODPD BIT(4)
512#define TB_LC_SX_CTRL_WOU4 BIT(5)
513#define TB_LC_SX_CTRL_WOP BIT(6)
514#define TB_LC_SX_CTRL_L1C BIT(16)
515#define TB_LC_SX_CTRL_L1D BIT(17)
516#define TB_LC_SX_CTRL_L2C BIT(20)
517#define TB_LC_SX_CTRL_L2D BIT(21)
518#define TB_LC_SX_CTRL_SLI BIT(29)
519#define TB_LC_SX_CTRL_UPSTREAM BIT(30)
520#define TB_LC_SX_CTRL_SLP BIT(31)
521#define TB_LC_LINK_ATTR 0x97
522#define TB_LC_LINK_ATTR_CPS BIT(18)
487
488#endif
523
524#endif