nhi.c (943795219d3cb9f8ce6ce51cad3ffe1f61e95c6b) nhi.c (3cdb9446a117d5d63af823bde6fe6babc312e77b)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Thunderbolt driver - NHI driver
4 *
5 * The NHI (native host interface) is the pci device that allows us to send and
6 * receive frames from the thunderbolt bus.
7 *
8 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
9 * Copyright (C) 2018, Intel Corporation
10 */
11
12#include <linux/pm_runtime.h>
13#include <linux/slab.h>
14#include <linux/errno.h>
15#include <linux/pci.h>
16#include <linux/interrupt.h>
17#include <linux/module.h>
18#include <linux/delay.h>
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Thunderbolt driver - NHI driver
4 *
5 * The NHI (native host interface) is the pci device that allows us to send and
6 * receive frames from the thunderbolt bus.
7 *
8 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
9 * Copyright (C) 2018, Intel Corporation
10 */
11
12#include <linux/pm_runtime.h>
13#include <linux/slab.h>
14#include <linux/errno.h>
15#include <linux/pci.h>
16#include <linux/interrupt.h>
17#include <linux/module.h>
18#include <linux/delay.h>
19#include <linux/property.h>
19
20#include "nhi.h"
21#include "nhi_regs.h"
22#include "tb.h"
23
24#define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring")
25
26/*

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854
855static irqreturn_t nhi_msi(int irq, void *data)
856{
857 struct tb_nhi *nhi = data;
858 schedule_work(&nhi->interrupt_work);
859 return IRQ_HANDLED;
860}
861
20
21#include "nhi.h"
22#include "nhi_regs.h"
23#include "tb.h"
24
25#define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring")
26
27/*

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855
856static irqreturn_t nhi_msi(int irq, void *data)
857{
858 struct tb_nhi *nhi = data;
859 schedule_work(&nhi->interrupt_work);
860 return IRQ_HANDLED;
861}
862
862static int nhi_suspend_noirq(struct device *dev)
863static int __nhi_suspend_noirq(struct device *dev, bool wakeup)
863{
864 struct pci_dev *pdev = to_pci_dev(dev);
865 struct tb *tb = pci_get_drvdata(pdev);
864{
865 struct pci_dev *pdev = to_pci_dev(dev);
866 struct tb *tb = pci_get_drvdata(pdev);
867 struct tb_nhi *nhi = tb->nhi;
868 int ret;
866
869
867 return tb_domain_suspend_noirq(tb);
870 ret = tb_domain_suspend_noirq(tb);
871 if (ret)
872 return ret;
873
874 if (nhi->ops && nhi->ops->suspend_noirq) {
875 ret = nhi->ops->suspend_noirq(tb->nhi, wakeup);
876 if (ret)
877 return ret;
878 }
879
880 return 0;
868}
869
881}
882
883static int nhi_suspend_noirq(struct device *dev)
884{
885 return __nhi_suspend_noirq(dev, device_may_wakeup(dev));
886}
887
888static bool nhi_wake_supported(struct pci_dev *pdev)
889{
890 u8 val;
891
892 /*
893 * If power rails are sustainable for wakeup from S4 this
894 * property is set by the BIOS.
895 */
896 if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val))
897 return !!val;
898
899 return true;
900}
901
902static int nhi_poweroff_noirq(struct device *dev)
903{
904 struct pci_dev *pdev = to_pci_dev(dev);
905 bool wakeup;
906
907 wakeup = device_may_wakeup(dev) && nhi_wake_supported(pdev);
908 return __nhi_suspend_noirq(dev, wakeup);
909}
910
870static void nhi_enable_int_throttling(struct tb_nhi *nhi)
871{
872 /* Throttling is specified in 256ns increments */
873 u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256);
874 unsigned int i;
875
876 /*
877 * Configure interrupt throttling for all vectors even if we

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882 iowrite32(throttle, nhi->iobase + reg);
883 }
884}
885
886static int nhi_resume_noirq(struct device *dev)
887{
888 struct pci_dev *pdev = to_pci_dev(dev);
889 struct tb *tb = pci_get_drvdata(pdev);
911static void nhi_enable_int_throttling(struct tb_nhi *nhi)
912{
913 /* Throttling is specified in 256ns increments */
914 u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256);
915 unsigned int i;
916
917 /*
918 * Configure interrupt throttling for all vectors even if we

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923 iowrite32(throttle, nhi->iobase + reg);
924 }
925}
926
927static int nhi_resume_noirq(struct device *dev)
928{
929 struct pci_dev *pdev = to_pci_dev(dev);
930 struct tb *tb = pci_get_drvdata(pdev);
931 struct tb_nhi *nhi = tb->nhi;
932 int ret;
890
891 /*
892 * Check that the device is still there. It may be that the user
893 * unplugged last device which causes the host controller to go
894 * away on PCs.
895 */
933
934 /*
935 * Check that the device is still there. It may be that the user
936 * unplugged last device which causes the host controller to go
937 * away on PCs.
938 */
896 if (!pci_device_is_present(pdev))
897 tb->nhi->going_away = true;
898 else
939 if (!pci_device_is_present(pdev)) {
940 nhi->going_away = true;
941 } else {
942 if (nhi->ops && nhi->ops->resume_noirq) {
943 ret = nhi->ops->resume_noirq(nhi);
944 if (ret)
945 return ret;
946 }
899 nhi_enable_int_throttling(tb->nhi);
947 nhi_enable_int_throttling(tb->nhi);
948 }
900
901 return tb_domain_resume_noirq(tb);
902}
903
904static int nhi_suspend(struct device *dev)
905{
906 struct pci_dev *pdev = to_pci_dev(dev);
907 struct tb *tb = pci_get_drvdata(pdev);

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924 else
925 tb_domain_complete(tb);
926}
927
928static int nhi_runtime_suspend(struct device *dev)
929{
930 struct pci_dev *pdev = to_pci_dev(dev);
931 struct tb *tb = pci_get_drvdata(pdev);
949
950 return tb_domain_resume_noirq(tb);
951}
952
953static int nhi_suspend(struct device *dev)
954{
955 struct pci_dev *pdev = to_pci_dev(dev);
956 struct tb *tb = pci_get_drvdata(pdev);

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973 else
974 tb_domain_complete(tb);
975}
976
977static int nhi_runtime_suspend(struct device *dev)
978{
979 struct pci_dev *pdev = to_pci_dev(dev);
980 struct tb *tb = pci_get_drvdata(pdev);
981 struct tb_nhi *nhi = tb->nhi;
982 int ret;
932
983
933 return tb_domain_runtime_suspend(tb);
984 ret = tb_domain_runtime_suspend(tb);
985 if (ret)
986 return ret;
987
988 if (nhi->ops && nhi->ops->runtime_suspend) {
989 ret = nhi->ops->runtime_suspend(tb->nhi);
990 if (ret)
991 return ret;
992 }
993 return 0;
934}
935
936static int nhi_runtime_resume(struct device *dev)
937{
938 struct pci_dev *pdev = to_pci_dev(dev);
939 struct tb *tb = pci_get_drvdata(pdev);
994}
995
996static int nhi_runtime_resume(struct device *dev)
997{
998 struct pci_dev *pdev = to_pci_dev(dev);
999 struct tb *tb = pci_get_drvdata(pdev);
1000 struct tb_nhi *nhi = tb->nhi;
1001 int ret;
940
1002
941 nhi_enable_int_throttling(tb->nhi);
1003 if (nhi->ops && nhi->ops->runtime_resume) {
1004 ret = nhi->ops->runtime_resume(nhi);
1005 if (ret)
1006 return ret;
1007 }
1008
1009 nhi_enable_int_throttling(nhi);
942 return tb_domain_runtime_resume(tb);
943}
944
945static void nhi_shutdown(struct tb_nhi *nhi)
946{
947 int i;
948
949 dev_dbg(&nhi->pdev->dev, "shutdown\n");

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961 * We have to release the irq before calling flush_work. Otherwise an
962 * already executing IRQ handler could call schedule_work again.
963 */
964 if (!nhi->pdev->msix_enabled) {
965 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi);
966 flush_work(&nhi->interrupt_work);
967 }
968 ida_destroy(&nhi->msix_ida);
1010 return tb_domain_runtime_resume(tb);
1011}
1012
1013static void nhi_shutdown(struct tb_nhi *nhi)
1014{
1015 int i;
1016
1017 dev_dbg(&nhi->pdev->dev, "shutdown\n");

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1029 * We have to release the irq before calling flush_work. Otherwise an
1030 * already executing IRQ handler could call schedule_work again.
1031 */
1032 if (!nhi->pdev->msix_enabled) {
1033 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi);
1034 flush_work(&nhi->interrupt_work);
1035 }
1036 ida_destroy(&nhi->msix_ida);
1037
1038 if (nhi->ops && nhi->ops->shutdown)
1039 nhi->ops->shutdown(nhi);
969}
970
971static int nhi_init_msi(struct tb_nhi *nhi)
972{
973 struct pci_dev *pdev = nhi->pdev;
974 int res, irq, nvec;
975
976 /* In case someone left them on. */

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1005 dev_err(&pdev->dev, "request_irq failed, aborting\n");
1006 return res;
1007 }
1008 }
1009
1010 return 0;
1011}
1012
1040}
1041
1042static int nhi_init_msi(struct tb_nhi *nhi)
1043{
1044 struct pci_dev *pdev = nhi->pdev;
1045 int res, irq, nvec;
1046
1047 /* In case someone left them on. */

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1076 dev_err(&pdev->dev, "request_irq failed, aborting\n");
1077 return res;
1078 }
1079 }
1080
1081 return 0;
1082}
1083
1084static bool nhi_imr_valid(struct pci_dev *pdev)
1085{
1086 u8 val;
1087
1088 if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val))
1089 return !!val;
1090
1091 return true;
1092}
1093
1013static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1014{
1015 struct tb_nhi *nhi;
1016 struct tb *tb;
1017 int res;
1018
1094static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1095{
1096 struct tb_nhi *nhi;
1097 struct tb *tb;
1098 int res;
1099
1100 if (!nhi_imr_valid(pdev)) {
1101 dev_warn(&pdev->dev, "firmware image not valid, aborting\n");
1102 return -ENODEV;
1103 }
1104
1019 res = pcim_enable_device(pdev);
1020 if (res) {
1021 dev_err(&pdev->dev, "cannot enable PCI device, aborting\n");
1022 return res;
1023 }
1024
1025 res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt");
1026 if (res) {
1027 dev_err(&pdev->dev, "cannot obtain PCI resources, aborting\n");
1028 return res;
1029 }
1030
1031 nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL);
1032 if (!nhi)
1033 return -ENOMEM;
1034
1035 nhi->pdev = pdev;
1105 res = pcim_enable_device(pdev);
1106 if (res) {
1107 dev_err(&pdev->dev, "cannot enable PCI device, aborting\n");
1108 return res;
1109 }
1110
1111 res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt");
1112 if (res) {
1113 dev_err(&pdev->dev, "cannot obtain PCI resources, aborting\n");
1114 return res;
1115 }
1116
1117 nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL);
1118 if (!nhi)
1119 return -ENOMEM;
1120
1121 nhi->pdev = pdev;
1122 nhi->ops = (const struct tb_nhi_ops *)id->driver_data;
1036 /* cannot fail - table is allocated bin pcim_iomap_regions */
1037 nhi->iobase = pcim_iomap_table(pdev)[0];
1038 nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff;
1039 if (nhi->hop_count != 12 && nhi->hop_count != 32)
1040 dev_warn(&pdev->dev, "unexpected hop count: %d\n",
1041 nhi->hop_count);
1042
1043 nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,

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1060 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1061 if (res) {
1062 dev_err(&pdev->dev, "failed to set DMA mask\n");
1063 return res;
1064 }
1065
1066 pci_set_master(pdev);
1067
1123 /* cannot fail - table is allocated bin pcim_iomap_regions */
1124 nhi->iobase = pcim_iomap_table(pdev)[0];
1125 nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff;
1126 if (nhi->hop_count != 12 && nhi->hop_count != 32)
1127 dev_warn(&pdev->dev, "unexpected hop count: %d\n",
1128 nhi->hop_count);
1129
1130 nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count,

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1147 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1148 if (res) {
1149 dev_err(&pdev->dev, "failed to set DMA mask\n");
1150 return res;
1151 }
1152
1153 pci_set_master(pdev);
1154
1155 if (nhi->ops && nhi->ops->init) {
1156 res = nhi->ops->init(nhi);
1157 if (res)
1158 return res;
1159 }
1160
1068 tb = icm_probe(nhi);
1069 if (!tb)
1070 tb = tb_probe(nhi);
1071 if (!tb) {
1072 dev_err(&nhi->pdev->dev,
1073 "failed to determine connection manager, aborting\n");
1074 return -ENODEV;
1075 }

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1120 .freeze_noirq = nhi_suspend_noirq, /*
1121 * we just disable hotplug, the
1122 * pci-tunnels stay alive.
1123 */
1124 .thaw_noirq = nhi_resume_noirq,
1125 .restore_noirq = nhi_resume_noirq,
1126 .suspend = nhi_suspend,
1127 .freeze = nhi_suspend,
1161 tb = icm_probe(nhi);
1162 if (!tb)
1163 tb = tb_probe(nhi);
1164 if (!tb) {
1165 dev_err(&nhi->pdev->dev,
1166 "failed to determine connection manager, aborting\n");
1167 return -ENODEV;
1168 }

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1213 .freeze_noirq = nhi_suspend_noirq, /*
1214 * we just disable hotplug, the
1215 * pci-tunnels stay alive.
1216 */
1217 .thaw_noirq = nhi_resume_noirq,
1218 .restore_noirq = nhi_resume_noirq,
1219 .suspend = nhi_suspend,
1220 .freeze = nhi_suspend,
1221 .poweroff_noirq = nhi_poweroff_noirq,
1128 .poweroff = nhi_suspend,
1129 .complete = nhi_complete,
1130 .runtime_suspend = nhi_runtime_suspend,
1131 .runtime_resume = nhi_runtime_resume,
1132};
1133
1134static struct pci_device_id nhi_ids[] = {
1135 /*

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1167 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) },
1168 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) },
1169 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) },
1170 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) },
1171 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) },
1172 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) },
1173 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) },
1174 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) },
1222 .poweroff = nhi_suspend,
1223 .complete = nhi_complete,
1224 .runtime_suspend = nhi_runtime_suspend,
1225 .runtime_resume = nhi_runtime_resume,
1226};
1227
1228static struct pci_device_id nhi_ids[] = {
1229 /*

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1261 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) },
1262 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) },
1263 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) },
1264 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) },
1265 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) },
1266 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) },
1267 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) },
1268 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) },
1269 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0),
1270 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1271 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1),
1272 .driver_data = (kernel_ulong_t)&icl_nhi_ops },
1175
1176 { 0,}
1177};
1178
1179MODULE_DEVICE_TABLE(pci, nhi_ids);
1180MODULE_LICENSE("GPL");
1181
1182static struct pci_driver nhi_driver = {

--- 28 unchanged lines hidden ---
1273
1274 { 0,}
1275};
1276
1277MODULE_DEVICE_TABLE(pci, nhi_ids);
1278MODULE_LICENSE("GPL");
1279
1280static struct pci_driver nhi_driver = {

--- 28 unchanged lines hidden ---