tegra124-soctherm.c (0cce284537fb42d9c28b9b31038ffc9b464555f5) tegra124-soctherm.c (5c9d6ac23170e672101bce965a8180af24c40adb)
1// SPDX-License-Identifier: GPL-2.0
1/*
2/*
2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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50 .pdiv = 8,
51 .pdiv_ate = 8,
52 .pdiv_mask = SENSOR_PDIV_CPU_MASK,
53 .pllx_hotspot_diff = 10,
54 .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
55 .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
56 .thermtrip_enable_mask = TEGRA124_THERMTRIP_CPU_EN_MASK,
57 .thermtrip_threshold_mask = TEGRA124_THERMTRIP_CPU_THRESH_MASK,
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

--- 39 unchanged lines hidden (view full) ---

51 .pdiv = 8,
52 .pdiv_ate = 8,
53 .pdiv_mask = SENSOR_PDIV_CPU_MASK,
54 .pllx_hotspot_diff = 10,
55 .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
56 .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
57 .thermtrip_enable_mask = TEGRA124_THERMTRIP_CPU_EN_MASK,
58 .thermtrip_threshold_mask = TEGRA124_THERMTRIP_CPU_THRESH_MASK,
59 .thermctl_isr_mask = THERM_IRQ_CPU_MASK,
58 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
59 .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
60 .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
61};
62
63static const struct tegra_tsensor_group tegra124_tsensor_group_gpu = {
64 .id = TEGRA124_SOCTHERM_SENSOR_GPU,
65 .name = "gpu",
66 .sensor_temp_offset = SENSOR_TEMP1,
67 .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
68 .pdiv = 8,
69 .pdiv_ate = 8,
70 .pdiv_mask = SENSOR_PDIV_GPU_MASK,
71 .pllx_hotspot_diff = 5,
72 .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
73 .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
74 .thermtrip_enable_mask = TEGRA124_THERMTRIP_GPU_EN_MASK,
75 .thermtrip_threshold_mask = TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK,
60 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
61 .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
62 .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
63};
64
65static const struct tegra_tsensor_group tegra124_tsensor_group_gpu = {
66 .id = TEGRA124_SOCTHERM_SENSOR_GPU,
67 .name = "gpu",
68 .sensor_temp_offset = SENSOR_TEMP1,
69 .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
70 .pdiv = 8,
71 .pdiv_ate = 8,
72 .pdiv_mask = SENSOR_PDIV_GPU_MASK,
73 .pllx_hotspot_diff = 5,
74 .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
75 .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
76 .thermtrip_enable_mask = TEGRA124_THERMTRIP_GPU_EN_MASK,
77 .thermtrip_threshold_mask = TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK,
78 .thermctl_isr_mask = THERM_IRQ_GPU_MASK,
76 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
77 .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
78 .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
79};
80
81static const struct tegra_tsensor_group tegra124_tsensor_group_pll = {
82 .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
83 .name = "pll",
84 .sensor_temp_offset = SENSOR_TEMP2,
85 .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
86 .pdiv = 8,
87 .pdiv_ate = 8,
88 .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
89 .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
90 .thermtrip_enable_mask = TEGRA124_THERMTRIP_TSENSE_EN_MASK,
91 .thermtrip_threshold_mask = TEGRA124_THERMTRIP_TSENSE_THRESH_MASK,
79 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
80 .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
81 .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
82};
83
84static const struct tegra_tsensor_group tegra124_tsensor_group_pll = {
85 .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
86 .name = "pll",
87 .sensor_temp_offset = SENSOR_TEMP2,
88 .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
89 .pdiv = 8,
90 .pdiv_ate = 8,
91 .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
92 .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
93 .thermtrip_enable_mask = TEGRA124_THERMTRIP_TSENSE_EN_MASK,
94 .thermtrip_threshold_mask = TEGRA124_THERMTRIP_TSENSE_THRESH_MASK,
95 .thermctl_isr_mask = THERM_IRQ_TSENSE_MASK,
92 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
93 .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
94 .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
95};
96
97static const struct tegra_tsensor_group tegra124_tsensor_group_mem = {
98 .id = TEGRA124_SOCTHERM_SENSOR_MEM,
99 .name = "mem",
100 .sensor_temp_offset = SENSOR_TEMP2,
101 .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
102 .pdiv = 8,
103 .pdiv_ate = 8,
104 .pdiv_mask = SENSOR_PDIV_MEM_MASK,
105 .pllx_hotspot_diff = 0,
106 .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
107 .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
108 .thermtrip_enable_mask = TEGRA124_THERMTRIP_MEM_EN_MASK,
109 .thermtrip_threshold_mask = TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK,
96 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
97 .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
98 .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
99};
100
101static const struct tegra_tsensor_group tegra124_tsensor_group_mem = {
102 .id = TEGRA124_SOCTHERM_SENSOR_MEM,
103 .name = "mem",
104 .sensor_temp_offset = SENSOR_TEMP2,
105 .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
106 .pdiv = 8,
107 .pdiv_ate = 8,
108 .pdiv_mask = SENSOR_PDIV_MEM_MASK,
109 .pllx_hotspot_diff = 0,
110 .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
111 .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK,
112 .thermtrip_enable_mask = TEGRA124_THERMTRIP_MEM_EN_MASK,
113 .thermtrip_threshold_mask = TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK,
114 .thermctl_isr_mask = THERM_IRQ_MEM_MASK,
110 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
111 .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
112 .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
113};
114
115static const struct tegra_tsensor_group *tegra124_tsensor_groups[] = {
116 &tegra124_tsensor_group_cpu,
117 &tegra124_tsensor_group_gpu,

--- 97 unchanged lines hidden --- 		115 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
116 .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK,
117 .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK,
118};
119
120static const struct tegra_tsensor_group *tegra124_tsensor_groups[] = {
121 &tegra124_tsensor_group_cpu,
122 &tegra124_tsensor_group_gpu,

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