exynos_tmu.c (cebe7373a7e659d29e939ed2ce379b478684793c) exynos_tmu.c (f4dae7532c33380aa23ddcf83d0260bfdee48549)
1/*
2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
3 *
4 * Copyright (C) 2011 Samsung Electronics
5 * Donggeun Kim <dg77.kim@samsung.com>
6 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
7 *
8 * This program is free software; you can redistribute it and/or modify

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137 const struct exynos_tmu_registers *reg = pdata->registers;
138 unsigned int status, trim_info = 0, con;
139 unsigned int rising_threshold = 0, falling_threshold = 0;
140 int ret = 0, threshold_code, i, trigger_levs = 0;
141
142 mutex_lock(&data->lock);
143 clk_enable(data->clk);
144
1/*
2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
3 *
4 * Copyright (C) 2011 Samsung Electronics
5 * Donggeun Kim <dg77.kim@samsung.com>
6 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
7 *
8 * This program is free software; you can redistribute it and/or modify

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137 const struct exynos_tmu_registers *reg = pdata->registers;
138 unsigned int status, trim_info = 0, con;
139 unsigned int rising_threshold = 0, falling_threshold = 0;
140 int ret = 0, threshold_code, i, trigger_levs = 0;
141
142 mutex_lock(&data->lock);
143 clk_enable(data->clk);
144
145 status = readb(data->base + reg->tmu_status);
146 if (!status) {
147 ret = -EBUSY;
148 goto out;
145 if (TMU_SUPPORTS(pdata, READY_STATUS)) {
146 status = readb(data->base + reg->tmu_status);
147 if (!status) {
148 ret = -EBUSY;
149 goto out;
150 }
149 }
150
151 }
152
151 if (data->soc == SOC_ARCH_EXYNOS)
153 if (TMU_SUPPORTS(pdata, TRIM_RELOAD))
152 __raw_writel(1, data->base + reg->triminfo_ctrl);
153
154 /* Save trimming info in order to perform calibration */
155 trim_info = readl(data->base + reg->triminfo_data);
156 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
157 data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
158 EXYNOS_TMU_TEMP_MASK);
159

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282
283 if (on) {
284 con |= (1 << reg->core_en_shift);
285 interrupt_en =
286 pdata->trigger_enable[3] << reg->inten_rise3_shift |
287 pdata->trigger_enable[2] << reg->inten_rise2_shift |
288 pdata->trigger_enable[1] << reg->inten_rise1_shift |
289 pdata->trigger_enable[0] << reg->inten_rise0_shift;
154 __raw_writel(1, data->base + reg->triminfo_ctrl);
155
156 /* Save trimming info in order to perform calibration */
157 trim_info = readl(data->base + reg->triminfo_data);
158 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
159 data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
160 EXYNOS_TMU_TEMP_MASK);
161

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284
285 if (on) {
286 con |= (1 << reg->core_en_shift);
287 interrupt_en =
288 pdata->trigger_enable[3] << reg->inten_rise3_shift |
289 pdata->trigger_enable[2] << reg->inten_rise2_shift |
290 pdata->trigger_enable[1] << reg->inten_rise1_shift |
291 pdata->trigger_enable[0] << reg->inten_rise0_shift;
290 if (pdata->threshold_falling)
292 if (TMU_SUPPORTS(pdata, FALLING_TRIP))
291 interrupt_en |=
292 interrupt_en << reg->inten_fall0_shift;
293 } else {
294 con &= ~(1 << reg->core_en_shift);
295 interrupt_en = 0; /* Disable all interrupts */
296 }
297 writel(interrupt_en, data->base + reg->tmu_inten);
298 writel(con, data->base + reg->tmu_ctrl);

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324static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
325{
326 struct exynos_tmu_data *data = drv_data;
327 struct exynos_tmu_platform_data *pdata = data->pdata;
328 const struct exynos_tmu_registers *reg = pdata->registers;
329 unsigned int val;
330 int ret = -EINVAL;
331
293 interrupt_en |=
294 interrupt_en << reg->inten_fall0_shift;
295 } else {
296 con &= ~(1 << reg->core_en_shift);
297 interrupt_en = 0; /* Disable all interrupts */
298 }
299 writel(interrupt_en, data->base + reg->tmu_inten);
300 writel(con, data->base + reg->tmu_ctrl);

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326static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
327{
328 struct exynos_tmu_data *data = drv_data;
329 struct exynos_tmu_platform_data *pdata = data->pdata;
330 const struct exynos_tmu_registers *reg = pdata->registers;
331 unsigned int val;
332 int ret = -EINVAL;
333
332 if (data->soc == SOC_ARCH_EXYNOS4210)
334 if (!TMU_SUPPORTS(pdata, EMULATION))
333 goto out;
334
335 if (temp && temp < MCELSIUS)
336 goto out;
337
338 mutex_lock(&data->lock);
339 clk_enable(data->clk);
340
341 val = readl(data->base + reg->emul_con);
342
343 if (temp) {
344 temp /= MCELSIUS;
345
335 goto out;
336
337 if (temp && temp < MCELSIUS)
338 goto out;
339
340 mutex_lock(&data->lock);
341 clk_enable(data->clk);
342
343 val = readl(data->base + reg->emul_con);
344
345 if (temp) {
346 temp /= MCELSIUS;
347
346 val = (EXYNOS_EMUL_TIME << reg->emul_time_shift) |
347 (temp_to_code(data, temp)
348 << reg->emul_temp_shift) | EXYNOS_EMUL_ENABLE;
348 if (TMU_SUPPORTS(pdata, EMUL_TIME)) {
349 val &= ~(EXYNOS_EMUL_TIME_MASK << reg->emul_time_shift);
350 val |= (EXYNOS_EMUL_TIME << reg->emul_time_shift);
351 }
352 val &= ~(EXYNOS_EMUL_DATA_MASK << reg->emul_temp_shift);
353 val |= (temp_to_code(data, temp) << reg->emul_temp_shift) |
354 EXYNOS_EMUL_ENABLE;
349 } else {
350 val &= ~EXYNOS_EMUL_ENABLE;
351 }
352
353 writel(val, data->base + reg->emul_con);
354
355 clk_disable(data->clk);
356 mutex_unlock(&data->lock);

--- 284 unchanged lines hidden --- 		355 } else {
356 val &= ~EXYNOS_EMUL_ENABLE;
357 }
358
359 writel(val, data->base + reg->emul_con);
360
361 clk_disable(data->clk);
362 mutex_unlock(&data->lock);

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