exynos_tmu.c (97b3881b8bc5f49a276b5265539f244bf507f42d) exynos_tmu.c (aef27b658b43aab1239f8eece52ce505fda0ffd4)
1/*
2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
3 *
4 * Copyright (C) 2014 Samsung Electronics
5 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
6 * Lukasz Majewski <l.majewski@samsung.com>
7 *
8 * Copyright (C) 2011 Samsung Electronics

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281 return (temp_code - data->temp_error1) *
282 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) /
283 (data->temp_error2 - data->temp_error1) +
284 EXYNOS_FIRST_POINT_TRIM;
285}
286
287static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
288{
1/*
2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
3 *
4 * Copyright (C) 2014 Samsung Electronics
5 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
6 * Lukasz Majewski <l.majewski@samsung.com>
7 *
8 * Copyright (C) 2011 Samsung Electronics

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281 return (temp_code - data->temp_error1) *
282 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) /
283 (data->temp_error2 - data->temp_error1) +
284 EXYNOS_FIRST_POINT_TRIM;
285}
286
287static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
288{
289 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
289 u16 tmu_temp_mask =
290 (data->soc == SOC_ARCH_EXYNOS7) ? EXYNOS7_TMU_TEMP_MASK
291 : EXYNOS_TMU_TEMP_MASK;
292
293 data->temp_error1 = trim_info & tmu_temp_mask;
290 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
291 EXYNOS_TMU_TEMP_MASK);
292
293 if (!data->temp_error1 ||
294 (data->min_efuse_value > data->temp_error1) ||
295 (data->temp_error1 > data->max_efuse_value))
296 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK;
297

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587 struct thermal_zone_device *tz = data->tzd;
588 unsigned int trim_info;
589 unsigned int rising_threshold = 0, falling_threshold = 0;
590 int ret = 0, threshold_code, i;
591 int temp, temp_hist;
592 unsigned int reg_off, bit_off;
593
594 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
294 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
295 EXYNOS_TMU_TEMP_MASK);
296
297 if (!data->temp_error1 ||
298 (data->min_efuse_value > data->temp_error1) ||
299 (data->temp_error1 > data->max_efuse_value))
300 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK;
301

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591 struct thermal_zone_device *tz = data->tzd;
592 unsigned int trim_info;
593 unsigned int rising_threshold = 0, falling_threshold = 0;
594 int ret = 0, threshold_code, i;
595 int temp, temp_hist;
596 unsigned int reg_off, bit_off;
597
598 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
599 sanitize_temp_error(data, trim_info);
595
600
596 data->temp_error1 = trim_info & EXYNOS7_TMU_TEMP_MASK;
597 if (!data->temp_error1 ||
598 (data->min_efuse_value > data->temp_error1) ||
599 (data->temp_error1 > data->max_efuse_value))
600 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK;
601
602 /* Write temperature code for rising and falling threshold */
603 for (i = (of_thermal_get_ntrips(tz) - 1); i >= 0; i--) {
604 /*
605 * On exynos7 there are 4 rising and 4 falling threshold
606 * registers (0x50-0x5c and 0x60-0x6c respectively). Each
607 * register holds the value of two threshold levels (at bit
608 * offsets 0 and 16). Based on the fact that there are atmost
609 * eight possible trigger levels, calculate the register and

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601 /* Write temperature code for rising and falling threshold */
602 for (i = (of_thermal_get_ntrips(tz) - 1); i >= 0; i--) {
603 /*
604 * On exynos7 there are 4 rising and 4 falling threshold
605 * registers (0x50-0x5c and 0x60-0x6c respectively). Each
606 * register holds the value of two threshold levels (at bit
607 * offsets 0 and 16). Based on the fact that there are atmost
608 * eight possible trigger levels, calculate the register and

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