exynos_tmu.c (1fe391bf0234add380245dea2dd72220394fe5fd) exynos_tmu.c (3b6a1a805f342472a0e68e2a0eb1decaadf7fa02)
1/*
2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
3 *
1/*
2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
3 *
4 * Copyright (C) 2014 Samsung Electronics
5 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
6 * Lukasz Majewski <l.majewski@samsung.com>
7 *
4 * Copyright (C) 2011 Samsung Electronics
5 * Donggeun Kim <dg77.kim@samsung.com>
6 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.

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26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
31#include <linux/platform_device.h>
32#include <linux/regulator/consumer.h>
33
8 * Copyright (C) 2011 Samsung Electronics
9 * Donggeun Kim <dg77.kim@samsung.com>
10 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.

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30#include <linux/interrupt.h>
31#include <linux/module.h>
32#include <linux/of.h>
33#include <linux/of_address.h>
34#include <linux/of_irq.h>
35#include <linux/platform_device.h>
36#include <linux/regulator/consumer.h>
37
34#include "exynos_thermal_common.h"
35#include "exynos_tmu.h"
38#include "exynos_tmu.h"
39#include "../thermal_core.h"
36
37/* Exynos generic registers */
38#define EXYNOS_TMU_REG_TRIMINFO 0x0
39#define EXYNOS_TMU_REG_CONTROL 0x20
40#define EXYNOS_TMU_REG_STATUS 0x28
41#define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
42#define EXYNOS_TMU_REG_INTEN 0x70
43#define EXYNOS_TMU_REG_INTSTAT 0x74

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110#define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0
111#define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1
112#define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2
113#define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3
114#define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4
115#define EXYNOS5440_TMU_TH_RISE4_SHIFT 24
116#define EXYNOS5440_EFUSE_SWAP_OFFSET 8
117
40
41/* Exynos generic registers */
42#define EXYNOS_TMU_REG_TRIMINFO 0x0
43#define EXYNOS_TMU_REG_CONTROL 0x20
44#define EXYNOS_TMU_REG_STATUS 0x28
45#define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
46#define EXYNOS_TMU_REG_INTEN 0x70
47#define EXYNOS_TMU_REG_INTSTAT 0x74

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114#define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0
115#define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1
116#define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2
117#define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3
118#define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4
119#define EXYNOS5440_TMU_TH_RISE4_SHIFT 24
120#define EXYNOS5440_EFUSE_SWAP_OFFSET 8
121
122#define MCELSIUS 1000
118/**
119 * struct exynos_tmu_data : A structure to hold the private data of the TMU
120 driver
121 * @id: identifier of the one instance of the TMU controller.
122 * @pdata: pointer to the tmu platform/configuration data
123 * @base: base address of the single instance of the TMU controller.
124 * @base_second: base address of the common registers of the TMU controller.
125 * @irq: irq number of the TMU controller.

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145 void __iomem *base_second;
146 int irq;
147 enum soc_type soc;
148 struct work_struct irq_work;
149 struct mutex lock;
150 struct clk *clk, *clk_sec;
151 u8 temp_error1, temp_error2;
152 struct regulator *regulator;
123/**
124 * struct exynos_tmu_data : A structure to hold the private data of the TMU
125 driver
126 * @id: identifier of the one instance of the TMU controller.
127 * @pdata: pointer to the tmu platform/configuration data
128 * @base: base address of the single instance of the TMU controller.
129 * @base_second: base address of the common registers of the TMU controller.
130 * @irq: irq number of the TMU controller.

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150 void __iomem *base_second;
151 int irq;
152 enum soc_type soc;
153 struct work_struct irq_work;
154 struct mutex lock;
155 struct clk *clk, *clk_sec;
156 u8 temp_error1, temp_error2;
157 struct regulator *regulator;
153 struct thermal_sensor_conf *reg_conf;
158 struct thermal_zone_device *tzd;
159
154 int (*tmu_initialize)(struct platform_device *pdev);
155 void (*tmu_control)(struct platform_device *pdev, bool on);
156 int (*tmu_read)(struct exynos_tmu_data *data);
157 void (*tmu_set_emulation)(struct exynos_tmu_data *data,
158 unsigned long temp);
159 void (*tmu_clear_irqs)(struct exynos_tmu_data *data);
160};
161
160 int (*tmu_initialize)(struct platform_device *pdev);
161 void (*tmu_control)(struct platform_device *pdev, bool on);
162 int (*tmu_read)(struct exynos_tmu_data *data);
163 void (*tmu_set_emulation)(struct exynos_tmu_data *data,
164 unsigned long temp);
165 void (*tmu_clear_irqs)(struct exynos_tmu_data *data);
166};
167
168static void exynos_report_trigger(struct exynos_tmu_data *p)
169{
170 char data[10], *envp[] = { data, NULL };
171 struct thermal_zone_device *tz = p->tzd;
172 unsigned long temp;
173 unsigned int i;
174
175 if (!p) {
176 pr_err("Wrong temperature configuration data\n");
177 return;
178 }
179
180 thermal_zone_device_update(tz);
181
182 mutex_lock(&tz->lock);
183 /* Find the level for which trip happened */
184 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
185 tz->ops->get_trip_temp(tz, i, &temp);
186 if (tz->last_temperature < temp)
187 break;
188 }
189
190 snprintf(data, sizeof(data), "%u", i);
191 kobject_uevent_env(&tz->device.kobj, KOBJ_CHANGE, envp);
192 mutex_unlock(&tz->lock);
193}
194
162/*
163 * TMU treats temperature as a mapped temperature code.
164 * The temperature is converted differently depending on the calibration type.
165 */
166static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
167{
168 struct exynos_tmu_platform_data *pdata = data->pdata;
169 int temp_code;

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229 if (!data->temp_error2)
230 data->temp_error2 =
231 (pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
232 EXYNOS_TMU_TEMP_MASK;
233}
234
235static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling)
236{
195/*
196 * TMU treats temperature as a mapped temperature code.
197 * The temperature is converted differently depending on the calibration type.
198 */
199static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
200{
201 struct exynos_tmu_platform_data *pdata = data->pdata;
202 int temp_code;

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262 if (!data->temp_error2)
263 data->temp_error2 =
264 (pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
265 EXYNOS_TMU_TEMP_MASK;
266}
267
268static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling)
269{
237 struct exynos_tmu_platform_data *pdata = data->pdata;
270 struct thermal_zone_device *tz = data->tzd;
271 const struct thermal_trip * const trips =
272 of_thermal_get_trip_points(tz);
273 unsigned long temp;
238 int i;
239
274 int i;
275
240 for (i = 0; i < pdata->non_hw_trigger_levels; i++) {
241 u8 temp = pdata->trigger_levels[i];
276 if (!trips) {
277 pr_err("%s: Cannot get trip points from of-thermal.c!\n",
278 __func__);
279 return 0;
280 }
242
281
282 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
283 if (trips[i].type == THERMAL_TRIP_CRITICAL)
284 continue;
285
286 temp = trips[i].temperature / MCELSIUS;
243 if (falling)
287 if (falling)
244 temp -= pdata->threshold_falling;
288 temp -= (trips[i].hysteresis / MCELSIUS);
245 else
246 threshold &= ~(0xff << 8 * i);
247
248 threshold |= temp_to_code(data, temp) << 8 * i;
249 }
250
251 return threshold;
252}

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300 data->tmu_control(pdev, on);
301 clk_disable(data->clk);
302 mutex_unlock(&data->lock);
303}
304
305static int exynos4210_tmu_initialize(struct platform_device *pdev)
306{
307 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
289 else
290 threshold &= ~(0xff << 8 * i);
291
292 threshold |= temp_to_code(data, temp) << 8 * i;
293 }
294
295 return threshold;
296}

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344 data->tmu_control(pdev, on);
345 clk_disable(data->clk);
346 mutex_unlock(&data->lock);
347}
348
349static int exynos4210_tmu_initialize(struct platform_device *pdev)
350{
351 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
308 struct exynos_tmu_platform_data *pdata = data->pdata;
309 unsigned int status;
352 struct thermal_zone_device *tz = data->tzd;
353 const struct thermal_trip * const trips =
354 of_thermal_get_trip_points(tz);
310 int ret = 0, threshold_code, i;
355 int ret = 0, threshold_code, i;
356 unsigned long reference, temp;
357 unsigned int status;
311
358
359 if (!trips) {
360 pr_err("%s: Cannot get trip points from of-thermal.c!\n",
361 __func__);
362 ret = -ENODEV;
363 goto out;
364 }
365
312 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
313 if (!status) {
314 ret = -EBUSY;
315 goto out;
316 }
317
318 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));
319
320 /* Write temperature code for threshold */
366 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
367 if (!status) {
368 ret = -EBUSY;
369 goto out;
370 }
371
372 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));
373
374 /* Write temperature code for threshold */
321 threshold_code = temp_to_code(data, pdata->threshold);
375 reference = trips[0].temperature / MCELSIUS;
376 threshold_code = temp_to_code(data, reference);
377 if (threshold_code < 0) {
378 ret = threshold_code;
379 goto out;
380 }
322 writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
323
381 writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
382
324 for (i = 0; i < pdata->non_hw_trigger_levels; i++)
325 writeb(pdata->trigger_levels[i], data->base +
383 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
384 temp = trips[i].temperature / MCELSIUS;
385 writeb(temp - reference, data->base +
326 EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
386 EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
387 }
327
328 data->tmu_clear_irqs(data);
329out:
330 return ret;
331}
332
333static int exynos4412_tmu_initialize(struct platform_device *pdev)
334{
335 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
388
389 data->tmu_clear_irqs(data);
390out:
391 return ret;
392}
393
394static int exynos4412_tmu_initialize(struct platform_device *pdev)
395{
396 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
336 struct exynos_tmu_platform_data *pdata = data->pdata;
397 const struct thermal_trip * const trips =
398 of_thermal_get_trip_points(data->tzd);
337 unsigned int status, trim_info, con, ctrl, rising_threshold;
338 int ret = 0, threshold_code, i;
399 unsigned int status, trim_info, con, ctrl, rising_threshold;
400 int ret = 0, threshold_code, i;
401 unsigned long crit_temp = 0;
339
340 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
341 if (!status) {
342 ret = -EBUSY;
343 goto out;
344 }
345
346 if (data->soc == SOC_ARCH_EXYNOS3250 ||

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368 rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE);
369 rising_threshold = get_th_reg(data, rising_threshold, false);
370 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
371 writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL);
372
373 data->tmu_clear_irqs(data);
374
375 /* if last threshold limit is also present */
402
403 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
404 if (!status) {
405 ret = -EBUSY;
406 goto out;
407 }
408
409 if (data->soc == SOC_ARCH_EXYNOS3250 ||

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431 rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE);
432 rising_threshold = get_th_reg(data, rising_threshold, false);
433 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
434 writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL);
435
436 data->tmu_clear_irqs(data);
437
438 /* if last threshold limit is also present */
376 i = pdata->max_trigger_level - 1;
377 if (pdata->trigger_levels[i] && pdata->trigger_type[i] == HW_TRIP) {
378 threshold_code = temp_to_code(data, pdata->trigger_levels[i]);
379 /* 1-4 level to be assigned in th0 reg */
380 rising_threshold &= ~(0xff << 8 * i);
381 rising_threshold |= threshold_code << 8 * i;
382 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
383 con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
384 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
385 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
439 for (i = 0; i < of_thermal_get_ntrips(data->tzd); i++) {
440 if (trips[i].type == THERMAL_TRIP_CRITICAL) {
441 crit_temp = trips[i].temperature;
442 break;
443 }
386 }
444 }
445
446 if (i == of_thermal_get_ntrips(data->tzd)) {
447 pr_err("%s: No CRITICAL trip point defined at of-thermal.c!\n",
448 __func__);
449 ret = -EINVAL;
450 goto out;
451 }
452
453 threshold_code = temp_to_code(data, crit_temp / MCELSIUS);
454 /* 1-4 level to be assigned in th0 reg */
455 rising_threshold &= ~(0xff << 8 * i);
456 rising_threshold |= threshold_code << 8 * i;
457 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
458 con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
459 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
460 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
461
387out:
388 return ret;
389}
390
391static int exynos5440_tmu_initialize(struct platform_device *pdev)
392{
393 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
462out:
463 return ret;
464}
465
466static int exynos5440_tmu_initialize(struct platform_device *pdev)
467{
468 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
394 struct exynos_tmu_platform_data *pdata = data->pdata;
395 unsigned int trim_info = 0, con, rising_threshold;
469 unsigned int trim_info = 0, con, rising_threshold;
396 int ret = 0, threshold_code, i;
470 int ret = 0, threshold_code;
471 unsigned long crit_temp = 0;
397
398 /*
399 * For exynos5440 soc triminfo value is swapped between TMU0 and
400 * TMU2, so the below logic is needed.
401 */
402 switch (data->id) {
403 case 0:
404 trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET +

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417 rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0);
418 rising_threshold = get_th_reg(data, rising_threshold, false);
419 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0);
420 writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1);
421
422 data->tmu_clear_irqs(data);
423
424 /* if last threshold limit is also present */
472
473 /*
474 * For exynos5440 soc triminfo value is swapped between TMU0 and
475 * TMU2, so the below logic is needed.
476 */
477 switch (data->id) {
478 case 0:
479 trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET +

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492 rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0);
493 rising_threshold = get_th_reg(data, rising_threshold, false);
494 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0);
495 writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1);
496
497 data->tmu_clear_irqs(data);
498
499 /* if last threshold limit is also present */
425 i = pdata->max_trigger_level - 1;
426 if (pdata->trigger_levels[i] && pdata->trigger_type[i] == HW_TRIP) {
427 threshold_code = temp_to_code(data, pdata->trigger_levels[i]);
500 if (!data->tzd->ops->get_crit_temp(data->tzd, &crit_temp)) {
501 threshold_code = temp_to_code(data, crit_temp / MCELSIUS);
428 /* 5th level to be assigned in th2 reg */
429 rising_threshold =
430 threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;
431 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2);
432 con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL);
433 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
434 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
435 }
436 /* Clear the PMIN in the common TMU register */
437 if (!data->id)
438 writel(0, data->base_second + EXYNOS5440_TMU_PMIN);
439 return ret;
440}
441
442static void exynos4210_tmu_control(struct platform_device *pdev, bool on)
443{
444 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
502 /* 5th level to be assigned in th2 reg */
503 rising_threshold =
504 threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;
505 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2);
506 con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL);
507 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
508 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
509 }
510 /* Clear the PMIN in the common TMU register */
511 if (!data->id)
512 writel(0, data->base_second + EXYNOS5440_TMU_PMIN);
513 return ret;
514}
515
516static void exynos4210_tmu_control(struct platform_device *pdev, bool on)
517{
518 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
445 struct exynos_tmu_platform_data *pdata = data->pdata;
519 struct thermal_zone_device *tz = data->tzd;
446 unsigned int con, interrupt_en;
447
448 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
449
450 if (on) {
451 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
452 interrupt_en =
520 unsigned int con, interrupt_en;
521
522 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
523
524 if (on) {
525 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
526 interrupt_en =
453 pdata->trigger_enable[3] << EXYNOS_TMU_INTEN_RISE3_SHIFT |
454 pdata->trigger_enable[2] << EXYNOS_TMU_INTEN_RISE2_SHIFT |
455 pdata->trigger_enable[1] << EXYNOS_TMU_INTEN_RISE1_SHIFT |
456 pdata->trigger_enable[0] << EXYNOS_TMU_INTEN_RISE0_SHIFT;
527 (of_thermal_is_trip_valid(tz, 3)
528 << EXYNOS_TMU_INTEN_RISE3_SHIFT) |
529 (of_thermal_is_trip_valid(tz, 2)
530 << EXYNOS_TMU_INTEN_RISE2_SHIFT) |
531 (of_thermal_is_trip_valid(tz, 1)
532 << EXYNOS_TMU_INTEN_RISE1_SHIFT) |
533 (of_thermal_is_trip_valid(tz, 0)
534 << EXYNOS_TMU_INTEN_RISE0_SHIFT);
535
457 if (data->soc != SOC_ARCH_EXYNOS4210)
458 interrupt_en |=
459 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
460 } else {
461 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
462 interrupt_en = 0; /* Disable all interrupts */
463 }
464 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
465 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
466}
467
468static void exynos5440_tmu_control(struct platform_device *pdev, bool on)
469{
470 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
536 if (data->soc != SOC_ARCH_EXYNOS4210)
537 interrupt_en |=
538 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
539 } else {
540 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
541 interrupt_en = 0; /* Disable all interrupts */
542 }
543 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
544 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
545}
546
547static void exynos5440_tmu_control(struct platform_device *pdev, bool on)
548{
549 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
471 struct exynos_tmu_platform_data *pdata = data->pdata;
550 struct thermal_zone_device *tz = data->tzd;
472 unsigned int con, interrupt_en;
473
474 con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL));
475
476 if (on) {
477 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
478 interrupt_en =
551 unsigned int con, interrupt_en;
552
553 con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL));
554
555 if (on) {
556 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
557 interrupt_en =
479 pdata->trigger_enable[3] << EXYNOS5440_TMU_INTEN_RISE3_SHIFT |
480 pdata->trigger_enable[2] << EXYNOS5440_TMU_INTEN_RISE2_SHIFT |
481 pdata->trigger_enable[1] << EXYNOS5440_TMU_INTEN_RISE1_SHIFT |
482 pdata->trigger_enable[0] << EXYNOS5440_TMU_INTEN_RISE0_SHIFT;
483 interrupt_en |= interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT;
558 (of_thermal_is_trip_valid(tz, 3)
559 << EXYNOS5440_TMU_INTEN_RISE3_SHIFT) |
560 (of_thermal_is_trip_valid(tz, 2)
561 << EXYNOS5440_TMU_INTEN_RISE2_SHIFT) |
562 (of_thermal_is_trip_valid(tz, 1)
563 << EXYNOS5440_TMU_INTEN_RISE1_SHIFT) |
564 (of_thermal_is_trip_valid(tz, 0)
565 << EXYNOS5440_TMU_INTEN_RISE0_SHIFT);
566 interrupt_en |=
567 interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT;
484 } else {
485 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
486 interrupt_en = 0; /* Disable all interrupts */
487 }
488 writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN);
489 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
490}
491
568 } else {
569 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
570 interrupt_en = 0; /* Disable all interrupts */
571 }
572 writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN);
573 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
574}
575
492static int exynos_tmu_read(struct exynos_tmu_data *data)
576static int exynos_get_temp(void *p, long *temp)
493{
577{
494 int ret;
578 struct exynos_tmu_data *data = p;
495
579
580 if (!data)
581 return -EINVAL;
582
496 mutex_lock(&data->lock);
497 clk_enable(data->clk);
583 mutex_lock(&data->lock);
584 clk_enable(data->clk);
498 ret = data->tmu_read(data);
499 if (ret >= 0)
500 ret = code_to_temp(data, ret);
585
586 *temp = code_to_temp(data, data->tmu_read(data)) * MCELSIUS;
587
501 clk_disable(data->clk);
502 mutex_unlock(&data->lock);
503
588 clk_disable(data->clk);
589 mutex_unlock(&data->lock);
590
504 return ret;
591 return 0;
505}
506
507#ifdef CONFIG_THERMAL_EMULATION
508static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val,
509 unsigned long temp)
510{
511 if (temp) {
512 temp /= MCELSIUS;

--- 95 unchanged lines hidden (view full) ---

608 if (data->soc == SOC_ARCH_EXYNOS5440) {
609 val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS);
610 if (!((val_type >> data->id) & 0x1))
611 goto out;
612 }
613 if (!IS_ERR(data->clk_sec))
614 clk_disable(data->clk_sec);
615
592}
593
594#ifdef CONFIG_THERMAL_EMULATION
595static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val,
596 unsigned long temp)
597{
598 if (temp) {
599 temp /= MCELSIUS;

--- 95 unchanged lines hidden (view full) ---

695 if (data->soc == SOC_ARCH_EXYNOS5440) {
696 val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS);
697 if (!((val_type >> data->id) & 0x1))
698 goto out;
699 }
700 if (!IS_ERR(data->clk_sec))
701 clk_disable(data->clk_sec);
702
616 exynos_report_trigger(data->reg_conf);
703 exynos_report_trigger(data);
617 mutex_lock(&data->lock);
618 clk_enable(data->clk);
619
620 /* TODO: take action based on particular interrupt */
621 data->tmu_clear_irqs(data);
622
623 clk_disable(data->clk);
624 mutex_unlock(&data->lock);

--- 43 unchanged lines hidden (view full) ---

668 schedule_work(&data->irq_work);
669
670 return IRQ_HANDLED;
671}
672
673static const struct of_device_id exynos_tmu_match[] = {
674 {
675 .compatible = "samsung,exynos3250-tmu",
704 mutex_lock(&data->lock);
705 clk_enable(data->clk);
706
707 /* TODO: take action based on particular interrupt */
708 data->tmu_clear_irqs(data);
709
710 clk_disable(data->clk);
711 mutex_unlock(&data->lock);

--- 43 unchanged lines hidden (view full) ---

755 schedule_work(&data->irq_work);
756
757 return IRQ_HANDLED;
758}
759
760static const struct of_device_id exynos_tmu_match[] = {
761 {
762 .compatible = "samsung,exynos3250-tmu",
676 .data = &exynos3250_default_tmu_data,
677 },
678 {
679 .compatible = "samsung,exynos4210-tmu",
763 },
764 {
765 .compatible = "samsung,exynos4210-tmu",
680 .data = &exynos4210_default_tmu_data,
681 },
682 {
683 .compatible = "samsung,exynos4412-tmu",
766 },
767 {
768 .compatible = "samsung,exynos4412-tmu",
684 .data = &exynos4412_default_tmu_data,
685 },
686 {
687 .compatible = "samsung,exynos5250-tmu",
769 },
770 {
771 .compatible = "samsung,exynos5250-tmu",
688 .data = &exynos5250_default_tmu_data,
689 },
690 {
691 .compatible = "samsung,exynos5260-tmu",
772 },
773 {
774 .compatible = "samsung,exynos5260-tmu",
692 .data = &exynos5260_default_tmu_data,
693 },
694 {
695 .compatible = "samsung,exynos5420-tmu",
775 },
776 {
777 .compatible = "samsung,exynos5420-tmu",
696 .data = &exynos5420_default_tmu_data,
697 },
698 {
699 .compatible = "samsung,exynos5420-tmu-ext-triminfo",
778 },
779 {
780 .compatible = "samsung,exynos5420-tmu-ext-triminfo",
700 .data = &exynos5420_default_tmu_data,
701 },
702 {
703 .compatible = "samsung,exynos5440-tmu",
781 },
782 {
783 .compatible = "samsung,exynos5440-tmu",
704 .data = &exynos5440_default_tmu_data,
705 },
706 {},
707};
708MODULE_DEVICE_TABLE(of, exynos_tmu_match);
709
784 },
785 {},
786};
787MODULE_DEVICE_TABLE(of, exynos_tmu_match);
788
710static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
711 struct platform_device *pdev, int id)
789static int exynos_of_get_soc_type(struct device_node *np)
712{
790{
713 struct exynos_tmu_init_data *data_table;
714 struct exynos_tmu_platform_data *tmu_data;
715 const struct of_device_id *match;
791 if (of_device_is_compatible(np, "samsung,exynos3250-tmu"))
792 return SOC_ARCH_EXYNOS3250;
793 else if (of_device_is_compatible(np, "samsung,exynos4210-tmu"))
794 return SOC_ARCH_EXYNOS4210;
795 else if (of_device_is_compatible(np, "samsung,exynos4412-tmu"))
796 return SOC_ARCH_EXYNOS4412;
797 else if (of_device_is_compatible(np, "samsung,exynos5250-tmu"))
798 return SOC_ARCH_EXYNOS5250;
799 else if (of_device_is_compatible(np, "samsung,exynos5260-tmu"))
800 return SOC_ARCH_EXYNOS5260;
801 else if (of_device_is_compatible(np, "samsung,exynos5420-tmu"))
802 return SOC_ARCH_EXYNOS5420;
803 else if (of_device_is_compatible(np,
804 "samsung,exynos5420-tmu-ext-triminfo"))
805 return SOC_ARCH_EXYNOS5420_TRIMINFO;
806 else if (of_device_is_compatible(np, "samsung,exynos5440-tmu"))
807 return SOC_ARCH_EXYNOS5440;
716
808
717 match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
718 if (!match)
719 return NULL;
720 data_table = (struct exynos_tmu_init_data *) match->data;
721 if (!data_table || id >= data_table->tmu_count)
722 return NULL;
723 tmu_data = data_table->tmu_data;
724 return (struct exynos_tmu_platform_data *) (tmu_data + id);
809 return -EINVAL;
725}
726
810}
811
812static int exynos_of_sensor_conf(struct device_node *np,
813 struct exynos_tmu_platform_data *pdata)
814{
815 u32 value;
816 int ret;
817
818 of_node_get(np);
819
820 ret = of_property_read_u32(np, "samsung,tmu_gain", &value);
821 pdata->gain = (u8)value;
822 of_property_read_u32(np, "samsung,tmu_reference_voltage", &value);
823 pdata->reference_voltage = (u8)value;
824 of_property_read_u32(np, "samsung,tmu_noise_cancel_mode", &value);
825 pdata->noise_cancel_mode = (u8)value;
826
827 of_property_read_u32(np, "samsung,tmu_efuse_value",
828 &pdata->efuse_value);
829 of_property_read_u32(np, "samsung,tmu_min_efuse_value",
830 &pdata->min_efuse_value);
831 of_property_read_u32(np, "samsung,tmu_max_efuse_value",
832 &pdata->max_efuse_value);
833
834 of_property_read_u32(np, "samsung,tmu_first_point_trim", &value);
835 pdata->first_point_trim = (u8)value;
836 of_property_read_u32(np, "samsung,tmu_second_point_trim", &value);
837 pdata->second_point_trim = (u8)value;
838 of_property_read_u32(np, "samsung,tmu_default_temp_offset", &value);
839 pdata->default_temp_offset = (u8)value;
840
841 of_property_read_u32(np, "samsung,tmu_cal_type", &pdata->cal_type);
842 of_property_read_u32(np, "samsung,tmu_cal_mode", &pdata->cal_mode);
843
844 of_node_put(np);
845 return 0;
846}
847
727static int exynos_map_dt_data(struct platform_device *pdev)
728{
729 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
730 struct exynos_tmu_platform_data *pdata;
731 struct resource res;
732 int ret;
733
734 if (!data || !pdev->dev.of_node)

--- 31 unchanged lines hidden (view full) ---

766 }
767
768 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
769 if (!data->base) {
770 dev_err(&pdev->dev, "Failed to ioremap memory\n");
771 return -EADDRNOTAVAIL;
772 }
773
848static int exynos_map_dt_data(struct platform_device *pdev)
849{
850 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
851 struct exynos_tmu_platform_data *pdata;
852 struct resource res;
853 int ret;
854
855 if (!data || !pdev->dev.of_node)

--- 31 unchanged lines hidden (view full) ---

887 }
888
889 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
890 if (!data->base) {
891 dev_err(&pdev->dev, "Failed to ioremap memory\n");
892 return -EADDRNOTAVAIL;
893 }
894
774 pdata = exynos_get_driver_data(pdev, data->id);
775 if (!pdata) {
776 dev_err(&pdev->dev, "No platform init data supplied.\n");
777 return -ENODEV;
778 }
895 pdata = devm_kzalloc(&pdev->dev,
896 sizeof(struct exynos_tmu_platform_data),
897 GFP_KERNEL);
898 if (!pdata)
899 return -ENOMEM;
779
900
901 exynos_of_sensor_conf(pdev->dev.of_node, pdata);
780 data->pdata = pdata;
902 data->pdata = pdata;
781 data->soc = pdata->type;
903 data->soc = exynos_of_get_soc_type(pdev->dev.of_node);
782
783 switch (data->soc) {
784 case SOC_ARCH_EXYNOS4210:
785 data->tmu_initialize = exynos4210_tmu_initialize;
786 data->tmu_control = exynos4210_tmu_control;
787 data->tmu_read = exynos4210_tmu_read;
788 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
789 break;

--- 39 unchanged lines hidden (view full) ---

829 if (!data->base_second) {
830 dev_err(&pdev->dev, "Failed to ioremap memory\n");
831 return -ENOMEM;
832 }
833
834 return 0;
835}
836
904
905 switch (data->soc) {
906 case SOC_ARCH_EXYNOS4210:
907 data->tmu_initialize = exynos4210_tmu_initialize;
908 data->tmu_control = exynos4210_tmu_control;
909 data->tmu_read = exynos4210_tmu_read;
910 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
911 break;

--- 39 unchanged lines hidden (view full) ---

951 if (!data->base_second) {
952 dev_err(&pdev->dev, "Failed to ioremap memory\n");
953 return -ENOMEM;
954 }
955
956 return 0;
957}
958
959static struct thermal_zone_of_device_ops exynos_sensor_ops = {
960 .get_temp = exynos_get_temp,
961 .set_emul_temp = exynos_tmu_set_emulation,
962};
963
837static int exynos_tmu_probe(struct platform_device *pdev)
838{
964static int exynos_tmu_probe(struct platform_device *pdev)
965{
839 struct exynos_tmu_data *data;
840 struct exynos_tmu_platform_data *pdata;
966 struct exynos_tmu_platform_data *pdata;
841 struct thermal_sensor_conf *sensor_conf;
842 int ret, i;
967 struct exynos_tmu_data *data;
968 int ret;
843
844 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
845 GFP_KERNEL);
846 if (!data)
847 return -ENOMEM;
848
849 platform_set_drvdata(pdev, data);
850 mutex_init(&data->lock);
851
969
970 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
971 GFP_KERNEL);
972 if (!data)
973 return -ENOMEM;
974
975 platform_set_drvdata(pdev, data);
976 mutex_init(&data->lock);
977
978 data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data,
979 &exynos_sensor_ops);
980 if (IS_ERR(data->tzd)) {
981 pr_err("thermal: tz: %p ERROR\n", data->tzd);
982 return PTR_ERR(data->tzd);
983 }
852 ret = exynos_map_dt_data(pdev);
853 if (ret)
984 ret = exynos_map_dt_data(pdev);
985 if (ret)
854 return ret;
986 goto err_sensor;
855
856 pdata = data->pdata;
857
858 INIT_WORK(&data->irq_work, exynos_tmu_work);
859
860 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
861 if (IS_ERR(data->clk)) {
862 dev_err(&pdev->dev, "Failed to get clock\n");
987
988 pdata = data->pdata;
989
990 INIT_WORK(&data->irq_work, exynos_tmu_work);
991
992 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
993 if (IS_ERR(data->clk)) {
994 dev_err(&pdev->dev, "Failed to get clock\n");
863 return PTR_ERR(data->clk);
995 ret = PTR_ERR(data->clk);
996 goto err_sensor;
864 }
865
866 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
867 if (IS_ERR(data->clk_sec)) {
868 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
869 dev_err(&pdev->dev, "Failed to get triminfo clock\n");
997 }
998
999 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
1000 if (IS_ERR(data->clk_sec)) {
1001 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
1002 dev_err(&pdev->dev, "Failed to get triminfo clock\n");
870 return PTR_ERR(data->clk_sec);
1003 ret = PTR_ERR(data->clk_sec);
1004 goto err_sensor;
871 }
872 } else {
873 ret = clk_prepare(data->clk_sec);
874 if (ret) {
875 dev_err(&pdev->dev, "Failed to get clock\n");
1005 }
1006 } else {
1007 ret = clk_prepare(data->clk_sec);
1008 if (ret) {
1009 dev_err(&pdev->dev, "Failed to get clock\n");
876 return ret;
1010 goto err_sensor;
877 }
878 }
879
880 ret = clk_prepare(data->clk);
881 if (ret) {
882 dev_err(&pdev->dev, "Failed to get clock\n");
883 goto err_clk_sec;
884 }
885
886 ret = exynos_tmu_initialize(pdev);
887 if (ret) {
888 dev_err(&pdev->dev, "Failed to initialize TMU\n");
889 goto err_clk;
890 }
891
1011 }
1012 }
1013
1014 ret = clk_prepare(data->clk);
1015 if (ret) {
1016 dev_err(&pdev->dev, "Failed to get clock\n");
1017 goto err_clk_sec;
1018 }
1019
1020 ret = exynos_tmu_initialize(pdev);
1021 if (ret) {
1022 dev_err(&pdev->dev, "Failed to initialize TMU\n");
1023 goto err_clk;
1024 }
1025
892 exynos_tmu_control(pdev, true);
893
894 /* Allocate a structure to register with the exynos core thermal */
895 sensor_conf = devm_kzalloc(&pdev->dev,
896 sizeof(struct thermal_sensor_conf), GFP_KERNEL);
897 if (!sensor_conf) {
898 ret = -ENOMEM;
899 goto err_clk;
900 }
901 sprintf(sensor_conf->name, "therm_zone%d", data->id);
902 sensor_conf->read_temperature = (int (*)(void *))exynos_tmu_read;
903 sensor_conf->write_emul_temp =
904 (int (*)(void *, unsigned long))exynos_tmu_set_emulation;
905 sensor_conf->driver_data = data;
906 sensor_conf->trip_data.trip_count = pdata->trigger_enable[0] +
907 pdata->trigger_enable[1] + pdata->trigger_enable[2]+
908 pdata->trigger_enable[3];
909
910 for (i = 0; i < sensor_conf->trip_data.trip_count; i++) {
911 sensor_conf->trip_data.trip_val[i] =
912 pdata->threshold + pdata->trigger_levels[i];
913 sensor_conf->trip_data.trip_type[i] =
914 pdata->trigger_type[i];
915 }
916
917 sensor_conf->trip_data.trigger_falling = pdata->threshold_falling;
918
919 sensor_conf->dev = &pdev->dev;
920 /* Register the sensor with thermal management interface */
921 ret = exynos_register_thermal(sensor_conf);
922 if (ret) {
923 if (ret != -EPROBE_DEFER)
924 dev_err(&pdev->dev,
925 "Failed to register thermal interface: %d\n",
926 ret);
927 goto err_clk;
928 }
929 data->reg_conf = sensor_conf;
930
931 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
932 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
933 if (ret) {
934 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
935 goto err_clk;
936 }
937
1026 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
1027 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
1028 if (ret) {
1029 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
1030 goto err_clk;
1031 }
1032
1033 exynos_tmu_control(pdev, true);
938 return 0;
939err_clk:
940 clk_unprepare(data->clk);
941err_clk_sec:
942 if (!IS_ERR(data->clk_sec))
943 clk_unprepare(data->clk_sec);
1034 return 0;
1035err_clk:
1036 clk_unprepare(data->clk);
1037err_clk_sec:
1038 if (!IS_ERR(data->clk_sec))
1039 clk_unprepare(data->clk_sec);
1040err_sensor:
1041 thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd);
1042
944 return ret;
945}
946
947static int exynos_tmu_remove(struct platform_device *pdev)
948{
949 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
1043 return ret;
1044}
1045
1046static int exynos_tmu_remove(struct platform_device *pdev)
1047{
1048 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
1049 struct thermal_zone_device *tzd = data->tzd;
950
1050
951 exynos_unregister_thermal(data->reg_conf);
952
1051 thermal_zone_of_sensor_unregister(&pdev->dev, tzd);
953 exynos_tmu_control(pdev, false);
954
955 clk_unprepare(data->clk);
956 if (!IS_ERR(data->clk_sec))
957 clk_unprepare(data->clk_sec);
958
959 if (!IS_ERR(data->regulator))
960 regulator_disable(data->regulator);

--- 45 unchanged lines hidden --- 		1052 exynos_tmu_control(pdev, false);
1053
1054 clk_unprepare(data->clk);
1055 if (!IS_ERR(data->clk_sec))
1056 clk_unprepare(data->clk_sec);
1057
1058 if (!IS_ERR(data->regulator))
1059 regulator_disable(data->regulator);

--- 45 unchanged lines hidden ---