spi-sifive.c (50501936288d6a29d7ef78f25d00e33240fad45f) spi-sifive.c (8d9ae783fb706ae98db18d050201d96a9634bd45)
1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2018 SiFive, Inc.
4//
5// SiFive SPI controller driver (master mode only)
6//
7// Author: SiFive, Inc.
8// sifive@sifive.com

--- 114 unchanged lines hidden (view full) ---

123 SIFIVE_SPI_DELAY1_INTERCS(1) |
124 SIFIVE_SPI_DELAY1_INTERXFR(0));
125
126 /* Exit specialized memory-mapped SPI flash mode */
127 sifive_spi_write(spi, SIFIVE_SPI_REG_FCTRL, 0);
128}
129
130static int
1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2018 SiFive, Inc.
4//
5// SiFive SPI controller driver (master mode only)
6//
7// Author: SiFive, Inc.
8// sifive@sifive.com

--- 114 unchanged lines hidden (view full) ---

123 SIFIVE_SPI_DELAY1_INTERCS(1) |
124 SIFIVE_SPI_DELAY1_INTERXFR(0));
125
126 /* Exit specialized memory-mapped SPI flash mode */
127 sifive_spi_write(spi, SIFIVE_SPI_REG_FCTRL, 0);
128}
129
130static int
131sifive_spi_prepare_message(struct spi_master *master, struct spi_message *msg)
131sifive_spi_prepare_message(struct spi_controller *host, struct spi_message *msg)
132{
132{
133 struct sifive_spi *spi = spi_master_get_devdata(master);
133 struct sifive_spi *spi = spi_controller_get_devdata(host);
134 struct spi_device *device = msg->spi;
135
136 /* Update the chip select polarity */
137 if (device->mode & SPI_CS_HIGH)
138 spi->cs_inactive &= ~BIT(spi_get_chipselect(device, 0));
139 else
140 spi->cs_inactive |= BIT(spi_get_chipselect(device, 0));
141 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);

--- 5 unchanged lines hidden (view full) ---

147 sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE,
148 device->mode & SIFIVE_SPI_SCKMODE_MODE_MASK);
149
150 return 0;
151}
152
153static void sifive_spi_set_cs(struct spi_device *device, bool is_high)
154{
134 struct spi_device *device = msg->spi;
135
136 /* Update the chip select polarity */
137 if (device->mode & SPI_CS_HIGH)
138 spi->cs_inactive &= ~BIT(spi_get_chipselect(device, 0));
139 else
140 spi->cs_inactive |= BIT(spi_get_chipselect(device, 0));
141 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);

--- 5 unchanged lines hidden (view full) ---

147 sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE,
148 device->mode & SIFIVE_SPI_SCKMODE_MODE_MASK);
149
150 return 0;
151}
152
153static void sifive_spi_set_cs(struct spi_device *device, bool is_high)
154{
155 struct sifive_spi *spi = spi_master_get_devdata(device->master);
155 struct sifive_spi *spi = spi_controller_get_devdata(device->controller);
156
157 /* Reverse polarity is handled by SCMR/CPOL. Not inverted CS. */
158 if (device->mode & SPI_CS_HIGH)
159 is_high = !is_high;
160
161 sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE, is_high ?
162 SIFIVE_SPI_CSMODE_MODE_AUTO :
163 SIFIVE_SPI_CSMODE_MODE_HOLD);

--- 83 unchanged lines hidden (view full) ---

247{
248 u32 data = sifive_spi_read(spi, SIFIVE_SPI_REG_RXDATA);
249
250 WARN_ON_ONCE((data & SIFIVE_SPI_RXDATA_EMPTY) != 0);
251 *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
252}
253
254static int
156
157 /* Reverse polarity is handled by SCMR/CPOL. Not inverted CS. */
158 if (device->mode & SPI_CS_HIGH)
159 is_high = !is_high;
160
161 sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE, is_high ?
162 SIFIVE_SPI_CSMODE_MODE_AUTO :
163 SIFIVE_SPI_CSMODE_MODE_HOLD);

--- 83 unchanged lines hidden (view full) ---

247{
248 u32 data = sifive_spi_read(spi, SIFIVE_SPI_REG_RXDATA);
249
250 WARN_ON_ONCE((data & SIFIVE_SPI_RXDATA_EMPTY) != 0);
251 *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
252}
253
254static int
255sifive_spi_transfer_one(struct spi_master *master, struct spi_device *device,
255sifive_spi_transfer_one(struct spi_controller *host, struct spi_device *device,
256 struct spi_transfer *t)
257{
256 struct spi_transfer *t)
257{
258 struct sifive_spi *spi = spi_master_get_devdata(master);
258 struct sifive_spi *spi = spi_controller_get_devdata(host);
259 int poll = sifive_spi_prep_transfer(spi, device, t);
260 const u8 *tx_ptr = t->tx_buf;
261 u8 *rx_ptr = t->rx_buf;
262 unsigned int remaining_words = t->len;
263
264 while (remaining_words) {
265 unsigned int n_words = min(remaining_words, spi->fifo_depth);
266 unsigned int i;

--- 22 unchanged lines hidden (view full) ---

289 return 0;
290}
291
292static int sifive_spi_probe(struct platform_device *pdev)
293{
294 struct sifive_spi *spi;
295 int ret, irq, num_cs;
296 u32 cs_bits, max_bits_per_word;
259 int poll = sifive_spi_prep_transfer(spi, device, t);
260 const u8 *tx_ptr = t->tx_buf;
261 u8 *rx_ptr = t->rx_buf;
262 unsigned int remaining_words = t->len;
263
264 while (remaining_words) {
265 unsigned int n_words = min(remaining_words, spi->fifo_depth);
266 unsigned int i;

--- 22 unchanged lines hidden (view full) ---

289 return 0;
290}
291
292static int sifive_spi_probe(struct platform_device *pdev)
293{
294 struct sifive_spi *spi;
295 int ret, irq, num_cs;
296 u32 cs_bits, max_bits_per_word;
297 struct spi_master *master;
297 struct spi_controller *host;
298
298
299 master = spi_alloc_master(&pdev->dev, sizeof(struct sifive_spi));
300 if (!master) {
299 host = spi_alloc_host(&pdev->dev, sizeof(struct sifive_spi));
300 if (!host) {
301 dev_err(&pdev->dev, "out of memory\n");
302 return -ENOMEM;
303 }
304
301 dev_err(&pdev->dev, "out of memory\n");
302 return -ENOMEM;
303 }
304
305 spi = spi_master_get_devdata(master);
305 spi = spi_controller_get_devdata(host);
306 init_completion(&spi->done);
306 init_completion(&spi->done);
307 platform_set_drvdata(pdev, master);
307 platform_set_drvdata(pdev, host);
308
309 spi->regs = devm_platform_ioremap_resource(pdev, 0);
310 if (IS_ERR(spi->regs)) {
311 ret = PTR_ERR(spi->regs);
308
309 spi->regs = devm_platform_ioremap_resource(pdev, 0);
310 if (IS_ERR(spi->regs)) {
311 ret = PTR_ERR(spi->regs);
312 goto put_master;
312 goto put_host;
313 }
314
315 spi->clk = devm_clk_get(&pdev->dev, NULL);
316 if (IS_ERR(spi->clk)) {
317 dev_err(&pdev->dev, "Unable to find bus clock\n");
318 ret = PTR_ERR(spi->clk);
313 }
314
315 spi->clk = devm_clk_get(&pdev->dev, NULL);
316 if (IS_ERR(spi->clk)) {
317 dev_err(&pdev->dev, "Unable to find bus clock\n");
318 ret = PTR_ERR(spi->clk);
319 goto put_master;
319 goto put_host;
320 }
321
322 irq = platform_get_irq(pdev, 0);
323 if (irq < 0) {
324 ret = irq;
320 }
321
322 irq = platform_get_irq(pdev, 0);
323 if (irq < 0) {
324 ret = irq;
325 goto put_master;
325 goto put_host;
326 }
327
328 /* Optional parameters */
329 ret =
330 of_property_read_u32(pdev->dev.of_node, "sifive,fifo-depth",
331 &spi->fifo_depth);
332 if (ret < 0)
333 spi->fifo_depth = SIFIVE_SPI_DEFAULT_DEPTH;
334
335 ret =
336 of_property_read_u32(pdev->dev.of_node, "sifive,max-bits-per-word",
337 &max_bits_per_word);
338
339 if (!ret && max_bits_per_word < 8) {
340 dev_err(&pdev->dev, "Only 8bit SPI words supported by the driver\n");
341 ret = -EINVAL;
326 }
327
328 /* Optional parameters */
329 ret =
330 of_property_read_u32(pdev->dev.of_node, "sifive,fifo-depth",
331 &spi->fifo_depth);
332 if (ret < 0)
333 spi->fifo_depth = SIFIVE_SPI_DEFAULT_DEPTH;
334
335 ret =
336 of_property_read_u32(pdev->dev.of_node, "sifive,max-bits-per-word",
337 &max_bits_per_word);
338
339 if (!ret && max_bits_per_word < 8) {
340 dev_err(&pdev->dev, "Only 8bit SPI words supported by the driver\n");
341 ret = -EINVAL;
342 goto put_master;
342 goto put_host;
343 }
344
345 /* Spin up the bus clock before hitting registers */
346 ret = clk_prepare_enable(spi->clk);
347 if (ret) {
348 dev_err(&pdev->dev, "Unable to enable bus clock\n");
343 }
344
345 /* Spin up the bus clock before hitting registers */
346 ret = clk_prepare_enable(spi->clk);
347 if (ret) {
348 dev_err(&pdev->dev, "Unable to enable bus clock\n");
349 goto put_master;
349 goto put_host;
350 }
351
352 /* probe the number of CS lines */
353 spi->cs_inactive = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
354 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, 0xffffffffU);
355 cs_bits = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
356 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
357 if (!cs_bits) {
358 dev_err(&pdev->dev, "Could not auto probe CS lines\n");
359 ret = -EINVAL;
360 goto disable_clk;
361 }
362
363 num_cs = ilog2(cs_bits) + 1;
364 if (num_cs > SIFIVE_SPI_MAX_CS) {
350 }
351
352 /* probe the number of CS lines */
353 spi->cs_inactive = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
354 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, 0xffffffffU);
355 cs_bits = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
356 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
357 if (!cs_bits) {
358 dev_err(&pdev->dev, "Could not auto probe CS lines\n");
359 ret = -EINVAL;
360 goto disable_clk;
361 }
362
363 num_cs = ilog2(cs_bits) + 1;
364 if (num_cs > SIFIVE_SPI_MAX_CS) {
365 dev_err(&pdev->dev, "Invalid number of spi slaves\n");
365 dev_err(&pdev->dev, "Invalid number of spi targets\n");
366 ret = -EINVAL;
367 goto disable_clk;
368 }
369
366 ret = -EINVAL;
367 goto disable_clk;
368 }
369
370 /* Define our master */
371 master->dev.of_node = pdev->dev.of_node;
372 master->bus_num = pdev->id;
373 master->num_chipselect = num_cs;
374 master->mode_bits = SPI_CPHA | SPI_CPOL
370 /* Define our host */
371 host->dev.of_node = pdev->dev.of_node;
372 host->bus_num = pdev->id;
373 host->num_chipselect = num_cs;
374 host->mode_bits = SPI_CPHA | SPI_CPOL
375 | SPI_CS_HIGH | SPI_LSB_FIRST
376 | SPI_TX_DUAL | SPI_TX_QUAD
377 | SPI_RX_DUAL | SPI_RX_QUAD;
378 /* TODO: add driver support for bits_per_word < 8
379 * we need to "left-align" the bits (unless SPI_LSB_FIRST)
380 */
375 | SPI_CS_HIGH | SPI_LSB_FIRST
376 | SPI_TX_DUAL | SPI_TX_QUAD
377 | SPI_RX_DUAL | SPI_RX_QUAD;
378 /* TODO: add driver support for bits_per_word < 8
379 * we need to "left-align" the bits (unless SPI_LSB_FIRST)
380 */
381 master->bits_per_word_mask = SPI_BPW_MASK(8);
382 master->flags = SPI_CONTROLLER_MUST_TX | SPI_MASTER_GPIO_SS;
383 master->prepare_message = sifive_spi_prepare_message;
384 master->set_cs = sifive_spi_set_cs;
385 master->transfer_one = sifive_spi_transfer_one;
381 host->bits_per_word_mask = SPI_BPW_MASK(8);
382 host->flags = SPI_CONTROLLER_MUST_TX | SPI_CONTROLLER_GPIO_SS;
383 host->prepare_message = sifive_spi_prepare_message;
384 host->set_cs = sifive_spi_set_cs;
385 host->transfer_one = sifive_spi_transfer_one;
386
387 pdev->dev.dma_mask = NULL;
386
387 pdev->dev.dma_mask = NULL;
388 /* Configure the SPI master hardware */
388 /* Configure the SPI host hardware */
389 sifive_spi_init(spi);
390
391 /* Register for SPI Interrupt */
392 ret = devm_request_irq(&pdev->dev, irq, sifive_spi_irq, 0,
393 dev_name(&pdev->dev), spi);
394 if (ret) {
395 dev_err(&pdev->dev, "Unable to bind to interrupt\n");
396 goto disable_clk;
397 }
398
399 dev_info(&pdev->dev, "mapped; irq=%d, cs=%d\n",
389 sifive_spi_init(spi);
390
391 /* Register for SPI Interrupt */
392 ret = devm_request_irq(&pdev->dev, irq, sifive_spi_irq, 0,
393 dev_name(&pdev->dev), spi);
394 if (ret) {
395 dev_err(&pdev->dev, "Unable to bind to interrupt\n");
396 goto disable_clk;
397 }
398
399 dev_info(&pdev->dev, "mapped; irq=%d, cs=%d\n",
400 irq, master->num_chipselect);
400 irq, host->num_chipselect);
401
401
402 ret = devm_spi_register_master(&pdev->dev, master);
402 ret = devm_spi_register_controller(&pdev->dev, host);
403 if (ret < 0) {
403 if (ret < 0) {
404 dev_err(&pdev->dev, "spi_register_master failed\n");
404 dev_err(&pdev->dev, "spi_register_host failed\n");
405 goto disable_clk;
406 }
407
408 return 0;
409
410disable_clk:
411 clk_disable_unprepare(spi->clk);
405 goto disable_clk;
406 }
407
408 return 0;
409
410disable_clk:
411 clk_disable_unprepare(spi->clk);
412put_master:
413 spi_master_put(master);
412put_host:
413 spi_controller_put(host);
414
415 return ret;
416}
417
418static void sifive_spi_remove(struct platform_device *pdev)
419{
414
415 return ret;
416}
417
418static void sifive_spi_remove(struct platform_device *pdev)
419{
420 struct spi_master *master = platform_get_drvdata(pdev);
421 struct sifive_spi *spi = spi_master_get_devdata(master);
420 struct spi_controller *host = platform_get_drvdata(pdev);
421 struct sifive_spi *spi = spi_controller_get_devdata(host);
422
423 /* Disable all the interrupts just in case */
424 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
425 clk_disable_unprepare(spi->clk);
426}
427
428static int sifive_spi_suspend(struct device *dev)
429{
422
423 /* Disable all the interrupts just in case */
424 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
425 clk_disable_unprepare(spi->clk);
426}
427
428static int sifive_spi_suspend(struct device *dev)
429{
430 struct spi_master *master = dev_get_drvdata(dev);
431 struct sifive_spi *spi = spi_master_get_devdata(master);
430 struct spi_controller *host = dev_get_drvdata(dev);
431 struct sifive_spi *spi = spi_controller_get_devdata(host);
432 int ret;
433
432 int ret;
433
434 ret = spi_master_suspend(master);
434 ret = spi_controller_suspend(host);
435 if (ret)
436 return ret;
437
438 /* Disable all the interrupts just in case */
439 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
440
441 clk_disable_unprepare(spi->clk);
442
443 return ret;
444}
445
446static int sifive_spi_resume(struct device *dev)
447{
435 if (ret)
436 return ret;
437
438 /* Disable all the interrupts just in case */
439 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
440
441 clk_disable_unprepare(spi->clk);
442
443 return ret;
444}
445
446static int sifive_spi_resume(struct device *dev)
447{
448 struct spi_master *master = dev_get_drvdata(dev);
449 struct sifive_spi *spi = spi_master_get_devdata(master);
448 struct spi_controller *host = dev_get_drvdata(dev);
449 struct sifive_spi *spi = spi_controller_get_devdata(host);
450 int ret;
451
452 ret = clk_prepare_enable(spi->clk);
453 if (ret)
454 return ret;
450 int ret;
451
452 ret = clk_prepare_enable(spi->clk);
453 if (ret)
454 return ret;
455 ret = spi_master_resume(master);
455 ret = spi_controller_resume(host);
456 if (ret)
457 clk_disable_unprepare(spi->clk);
458
459 return ret;
460}
461
462static DEFINE_SIMPLE_DEV_PM_OPS(sifive_spi_pm_ops,
463 sifive_spi_suspend, sifive_spi_resume);

--- 22 unchanged lines hidden --- 		456 if (ret)
457 clk_disable_unprepare(spi->clk);
458
459 return ret;
460}
461
462static DEFINE_SIMPLE_DEV_PM_OPS(sifive_spi_pm_ops,
463 sifive_spi_suspend, sifive_spi_resume);

--- 22 unchanged lines hidden ---