spi-rockchip.c (0aea30a07ec6b50de0fc5f5b2ec34a68ead86b61) spi-rockchip.c (d5d933f09ac326aebad85bfb787cc786ad477711)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * Author: Addy Ke <addy.ke@rock-chips.com>
5 */
6
7#include <linux/clk.h>
8#include <linux/dmaengine.h>

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191
192 u8 n_bytes;
193 u8 rsd;
194
195 bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
196
197 bool slave_abort;
198 bool cs_inactive; /* spi slave tansmition stop when cs inactive */
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * Author: Addy Ke <addy.ke@rock-chips.com>
5 */
6
7#include <linux/clk.h>
8#include <linux/dmaengine.h>

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191
192 u8 n_bytes;
193 u8 rsd;
194
195 bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM];
196
197 bool slave_abort;
198 bool cs_inactive; /* spi slave tansmition stop when cs inactive */
199 bool cs_high_supported; /* native CS supports active-high polarity */
200
199 struct spi_transfer *xfer; /* Store xfer temporarily */
200};
201
202static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
203{
204 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
205}
206

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714 return xfer->len / bytes_per_word >= rs->fifo_len;
715}
716
717static int rockchip_spi_setup(struct spi_device *spi)
718{
719 struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
720 u32 cr0;
721
201 struct spi_transfer *xfer; /* Store xfer temporarily */
202};
203
204static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable)
205{
206 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
207}
208

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716 return xfer->len / bytes_per_word >= rs->fifo_len;
717}
718
719static int rockchip_spi_setup(struct spi_device *spi)
720{
721 struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller);
722 u32 cr0;
723
724 if (!spi->cs_gpiod && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) {
725 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n");
726 return -EINVAL;
727 }
728
722 pm_runtime_get_sync(rs->dev);
723
724 cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0);
725
726 cr0 &= ~(0x3 << CR0_SCPH_OFFSET);
727 cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
728 if (spi->mode & SPI_CS_HIGH && spi->chip_select <= 1)
729 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;

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894 if (ctlr->dma_tx && ctlr->dma_rx) {
895 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
896 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
897 ctlr->can_dma = rockchip_spi_can_dma;
898 }
899
900 switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
901 case ROCKCHIP_SPI_VER2_TYPE2:
729 pm_runtime_get_sync(rs->dev);
730
731 cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0);
732
733 cr0 &= ~(0x3 << CR0_SCPH_OFFSET);
734 cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET);
735 if (spi->mode & SPI_CS_HIGH && spi->chip_select <= 1)
736 cr0 |= BIT(spi->chip_select) << CR0_SOI_OFFSET;

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901 if (ctlr->dma_tx && ctlr->dma_rx) {
902 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR;
903 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR;
904 ctlr->can_dma = rockchip_spi_can_dma;
905 }
906
907 switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) {
908 case ROCKCHIP_SPI_VER2_TYPE2:
909 rs->cs_high_supported = true;
902 ctlr->mode_bits |= SPI_CS_HIGH;
903 if (ctlr->can_dma && slave_mode)
904 rs->cs_inactive = true;
905 else
906 rs->cs_inactive = false;
907 break;
908 default:
909 rs->cs_inactive = false;

--- 166 unchanged lines hidden --- 		910 ctlr->mode_bits |= SPI_CS_HIGH;
911 if (ctlr->can_dma && slave_mode)
912 rs->cs_inactive = true;
913 else
914 rs->cs_inactive = false;
915 break;
916 default:
917 rs->cs_inactive = false;

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