fuse-tegra30.c (85a3685852d9ac7d92be9d824533c915a4597fa4) fuse-tegra30.c (7e939de1b2bb26496e4967e5346619700245e7c0)
1/*
2 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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37#define FUSE_LOT_CODE_0 0x108
38#define FUSE_LOT_CODE_1 0x10c
39#define FUSE_WAFER_ID 0x110
40#define FUSE_X_COORDINATE 0x114
41#define FUSE_Y_COORDINATE 0x118
42
43#define FUSE_HAS_REVISION_INFO BIT(0)
44
1/*
2 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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37#define FUSE_LOT_CODE_0 0x108
38#define FUSE_LOT_CODE_1 0x10c
39#define FUSE_WAFER_ID 0x110
40#define FUSE_X_COORDINATE 0x114
41#define FUSE_Y_COORDINATE 0x118
42
43#define FUSE_HAS_REVISION_INFO BIT(0)
44
45enum speedo_idx {
46 SPEEDO_TEGRA30 = 0,
47 SPEEDO_TEGRA114,
48 SPEEDO_TEGRA124,
49};
50
51struct tegra_fuse_info {
52 int size;
53 int spare_bit;
54 enum speedo_idx speedo_idx;
55};
56
57static void __iomem *fuse_base;
58static struct clk *fuse_clk;
59static const struct tegra_fuse_info *fuse_info;
60
61u32 tegra30_fuse_readl(const unsigned int offset)
45#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
46 defined(CONFIG_ARCH_TEGRA_114_SOC) || \
47 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
48 defined(CONFIG_ARCH_TEGRA_132_SOC)
49static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
62{
50{
63 u32 val;
64
65 /*
66 * early in the boot, the fuse clock will be enabled by
67 * tegra_init_fuse()
68 */
69
70 if (fuse_clk)
71 clk_prepare_enable(fuse_clk);
72
73 val = readl_relaxed(fuse_base + FUSE_BEGIN + offset);
74
75 if (fuse_clk)
76 clk_disable_unprepare(fuse_clk);
77
78 return val;
51 return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
79}
80
52}
53
81static const struct tegra_fuse_info tegra30_info = {
82 .size = 0x2a4,
83 .spare_bit = 0x144,
84 .speedo_idx = SPEEDO_TEGRA30,
85};
86
87static const struct tegra_fuse_info tegra114_info = {
88 .size = 0x2a0,
89 .speedo_idx = SPEEDO_TEGRA114,
90};
91
92static const struct tegra_fuse_info tegra124_info = {
93 .size = 0x300,
94 .speedo_idx = SPEEDO_TEGRA124,
95};
96
97static const struct of_device_id tegra30_fuse_of_match[] = {
98 { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_info },
99 { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_info },
100 { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_info },
101 {},
102};
103
104static int tegra30_fuse_probe(struct platform_device *pdev)
54static u32 tegra30_fuse_read(struct tegra_fuse *fuse, unsigned int offset)
105{
55{
106 const struct of_device_id *of_dev_id;
56 u32 value;
57 int err;
107
58
108 of_dev_id = of_match_device(tegra30_fuse_of_match, &pdev->dev);
109 if (!of_dev_id)
110 return -ENODEV;
111
112 fuse_clk = devm_clk_get(&pdev->dev, NULL);
113 if (IS_ERR(fuse_clk)) {
114 dev_err(&pdev->dev, "missing clock");
115 return PTR_ERR(fuse_clk);
59 err = clk_prepare_enable(fuse->clk);
60 if (err < 0) {
61 dev_err(fuse->dev, "failed to enable FUSE clock: %d\n", err);
62 return 0;
116 }
117
63 }
64
118 platform_set_drvdata(pdev, NULL);
65 value = readl_relaxed(fuse->base + FUSE_BEGIN + offset);
119
66
120 if (tegra_fuse_create_sysfs(&pdev->dev, fuse_info->size,
121 tegra30_fuse_readl))
122 return -ENODEV;
67 clk_disable_unprepare(fuse->clk);
123
68
124 dev_dbg(&pdev->dev, "loaded\n");
125
126 return 0;
69 return value;
127}
128
70}
71
129static struct platform_driver tegra30_fuse_driver = {
130 .probe = tegra30_fuse_probe,
131 .driver = {
132 .name = "tegra_fuse",
133 .of_match_table = tegra30_fuse_of_match,
134 }
135};
136
137static int __init tegra30_fuse_init(void)
138{
139 return platform_driver_register(&tegra30_fuse_driver);
140}
141postcore_initcall(tegra30_fuse_init);
142
143/* Early boot code. This code is called before the devices are created */
144
145typedef void (*speedo_f)(struct tegra_sku_info *sku_info);
146
147static speedo_f __initdata speedo_tbl[] = {
148 [SPEEDO_TEGRA30] = tegra30_init_speedo_data,
149 [SPEEDO_TEGRA114] = tegra114_init_speedo_data,
150 [SPEEDO_TEGRA124] = tegra124_init_speedo_data,
151};
152
153static void __init tegra30_fuse_add_randomness(void)
154{
155 u32 randomness[12];
156
157 randomness[0] = tegra_sku_info.sku_id;
158 randomness[1] = tegra_read_straps();
159 randomness[2] = tegra_read_chipid();
160 randomness[3] = tegra_sku_info.cpu_process_id << 16;
161 randomness[3] |= tegra_sku_info.core_process_id;
162 randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
163 randomness[4] |= tegra_sku_info.soc_speedo_id;
72static void __init tegra30_fuse_add_randomness(void)
73{
74 u32 randomness[12];
75
76 randomness[0] = tegra_sku_info.sku_id;
77 randomness[1] = tegra_read_straps();
78 randomness[2] = tegra_read_chipid();
79 randomness[3] = tegra_sku_info.cpu_process_id << 16;
80 randomness[3] |= tegra_sku_info.core_process_id;
81 randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
82 randomness[4] |= tegra_sku_info.soc_speedo_id;
164 randomness[5] = tegra30_fuse_readl(FUSE_VENDOR_CODE);
165 randomness[6] = tegra30_fuse_readl(FUSE_FAB_CODE);
166 randomness[7] = tegra30_fuse_readl(FUSE_LOT_CODE_0);
167 randomness[8] = tegra30_fuse_readl(FUSE_LOT_CODE_1);
168 randomness[9] = tegra30_fuse_readl(FUSE_WAFER_ID);
169 randomness[10] = tegra30_fuse_readl(FUSE_X_COORDINATE);
170 randomness[11] = tegra30_fuse_readl(FUSE_Y_COORDINATE);
83 randomness[5] = tegra_fuse_read_early(FUSE_VENDOR_CODE);
84 randomness[6] = tegra_fuse_read_early(FUSE_FAB_CODE);
85 randomness[7] = tegra_fuse_read_early(FUSE_LOT_CODE_0);
86 randomness[8] = tegra_fuse_read_early(FUSE_LOT_CODE_1);
87 randomness[9] = tegra_fuse_read_early(FUSE_WAFER_ID);
88 randomness[10] = tegra_fuse_read_early(FUSE_X_COORDINATE);
89 randomness[11] = tegra_fuse_read_early(FUSE_Y_COORDINATE);
171
172 add_device_randomness(randomness, sizeof(randomness));
173}
174
90
91 add_device_randomness(randomness, sizeof(randomness));
92}
93
175static void __init legacy_fuse_init(void)
94static void __init tegra30_fuse_init(struct tegra_fuse *fuse)
176{
95{
177 switch (tegra_get_chip_id()) {
178 case TEGRA30:
179 fuse_info = &tegra30_info;
180 break;
181 case TEGRA114:
182 fuse_info = &tegra114_info;
183 break;
184 case TEGRA124:
185 case TEGRA132:
186 fuse_info = &tegra124_info;
187 break;
188 default:
189 return;
190 }
96 fuse->read_early = tegra30_fuse_read_early;
97 fuse->read = tegra30_fuse_read;
191
98
192 fuse_base = ioremap(TEGRA_FUSE_BASE, TEGRA_FUSE_SIZE);
99 tegra_init_revision();
100 fuse->soc->speedo_init(&tegra_sku_info);
101 tegra30_fuse_add_randomness();
193}
102}
103#endif
194
104
195bool __init tegra30_spare_fuse(int spare_bit)
196{
197 u32 offset = fuse_info->spare_bit + spare_bit * 4;
105#ifdef CONFIG_ARCH_TEGRA_3x_SOC
106static const struct tegra_fuse_info tegra30_fuse_info = {
107 .read = tegra30_fuse_read,
108 .size = 0x2a4,
109 .spare = 0x144,
110};
198
111
199 return tegra30_fuse_readl(offset) & 1;
200}
112const struct tegra_fuse_soc tegra30_fuse_soc = {
113 .init = tegra30_fuse_init,
114 .speedo_init = tegra30_init_speedo_data,
115 .info = &tegra30_fuse_info,
116};
117#endif
201
118
202void __init tegra30_init_fuse_early(void)
203{
204 struct device_node *np;
205 const struct of_device_id *of_match;
119#ifdef CONFIG_ARCH_TEGRA_114_SOC
120static const struct tegra_fuse_info tegra114_fuse_info = {
121 .read = tegra30_fuse_read,
122 .size = 0x2a0,
123};
206
124
207 np = of_find_matching_node_and_match(NULL, tegra30_fuse_of_match,
208 &of_match);
209 if (np) {
210 fuse_base = of_iomap(np, 0);
211 fuse_info = (struct tegra_fuse_info *)of_match->data;
212 } else
213 legacy_fuse_init();
125const struct tegra_fuse_soc tegra114_fuse_soc = {
126 .init = tegra30_fuse_init,
127 .speedo_init = tegra114_init_speedo_data,
128 .info = &tegra114_fuse_info,
129};
130#endif
214
131
215 if (!fuse_base) {
216 pr_warn("fuse DT node missing and unknown chip id: 0x%02x\n",
217 tegra_get_chip_id());
218 return;
219 }
132#if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
133static const struct tegra_fuse_info tegra124_fuse_info = {
134 .read = tegra30_fuse_read,
135 .size = 0x300,
136};
220
137
221 tegra_init_revision();
222 speedo_tbl[fuse_info->speedo_idx](&tegra_sku_info);
223 tegra30_fuse_add_randomness();
224}
138const struct tegra_fuse_soc tegra124_fuse_soc = {
139 .init = tegra30_fuse_init,
140 .speedo_init = tegra124_init_speedo_data,
141 .info = &tegra124_fuse_info,
142};
143#endif