exynos5420-pmu.c (6ea24cf79e055f0a62a64baa8587e2254a493c7b) exynos5420-pmu.c (aec6341e2ac76ea8703642e83535f216b8866162)
1/*
2 * Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * EXYNOS5420 - CPU PMU (Power Management Unit) support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/pm.h>
13#include <linux/soc/samsung/exynos-regs-pmu.h>
14#include <linux/soc/samsung/exynos-pmu.h>
15
16#include <asm/cputype.h>
17
18#include "exynos-pmu.h"
19
1/*
2 * Copyright (c) 2011-2015 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * EXYNOS5420 - CPU PMU (Power Management Unit) support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/pm.h>
13#include <linux/soc/samsung/exynos-regs-pmu.h>
14#include <linux/soc/samsung/exynos-pmu.h>
15
16#include <asm/cputype.h>
17
18#include "exynos-pmu.h"
19
20static struct exynos_pmu_conf exynos5420_pmu_config[] = {
20static const struct exynos_pmu_conf exynos5420_pmu_config[] = {
21 /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
22 { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
23 { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
24 { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
25 { EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
26 { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
27 { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
28 { EXYNOS5420_ARM_CORE2_SYS_PWR_REG, { 0x0, 0x0, 0x0} },

--- 252 unchanged lines hidden --- 		21 /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
22 { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
23 { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
24 { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
25 { EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
26 { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
27 { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} },
28 { EXYNOS5420_ARM_CORE2_SYS_PWR_REG, { 0x0, 0x0, 0x0} },

--- 252 unchanged lines hidden ---