k210-sysctl.c (08734e0581a54df77f1af354b93b02ac581e4fbb) k210-sysctl.c (802fee26d8afd073c630a74dbe1a996970f3fd90)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2019 Christoph Hellwig.
4 * Copyright (c) 2019 Western Digital Corporation or its affiliates.
5 */
6#include <linux/types.h>
7#include <linux/io.h>
8#include <linux/of.h>
9#include <linux/platform_device.h>
10#include <linux/clk-provider.h>
11#include <linux/clkdev.h>
12#include <linux/bitfield.h>
13#include <asm/soc.h>
14
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2019 Christoph Hellwig.
4 * Copyright (c) 2019 Western Digital Corporation or its affiliates.
5 */
6#include <linux/types.h>
7#include <linux/io.h>
8#include <linux/of.h>
9#include <linux/platform_device.h>
10#include <linux/clk-provider.h>
11#include <linux/clkdev.h>
12#include <linux/bitfield.h>
13#include <asm/soc.h>
14
15#include <soc/canaan/k210-sysctl.h>
16
15#define K210_SYSCTL_CLK0_FREQ 26000000UL
16
17/* Registers base address */
18#define K210_SYSCTL_SYSCTL_BASE_ADDR 0x50440000ULL
19
17#define K210_SYSCTL_CLK0_FREQ 26000000UL
18
19/* Registers base address */
20#define K210_SYSCTL_SYSCTL_BASE_ADDR 0x50440000ULL
21
20/* Registers */
21#define K210_SYSCTL_PLL0 0x08
22#define K210_SYSCTL_PLL1 0x0c
23/* clkr: 4bits, clkf1: 6bits, clkod: 4bits, bwadj: 4bits */
24#define PLL_RESET (1 << 20)
25#define PLL_PWR (1 << 21)
26#define PLL_INTFB (1 << 22)
27#define PLL_BYPASS (1 << 23)
28#define PLL_TEST (1 << 24)
29#define PLL_OUT_EN (1 << 25)
30#define PLL_TEST_EN (1 << 26)
31#define K210_SYSCTL_PLL_LOCK 0x18
32#define PLL0_LOCK1 (1 << 0)
33#define PLL0_LOCK2 (1 << 1)
34#define PLL0_SLIP_CLEAR (1 << 2)
35#define PLL0_TEST_CLK_OUT (1 << 3)
36#define PLL1_LOCK1 (1 << 8)
37#define PLL1_LOCK2 (1 << 9)
38#define PLL1_SLIP_CLEAR (1 << 10)
39#define PLL1_TEST_CLK_OUT (1 << 11)
40#define PLL2_LOCK1 (1 << 16)
41#define PLL2_LOCK2 (1 << 16)
42#define PLL2_SLIP_CLEAR (1 << 18)
43#define PLL2_TEST_CLK_OUT (1 << 19)
44#define K210_SYSCTL_CLKSEL0 0x20
45#define CLKSEL_ACLK (1 << 0)
46#define K210_SYSCTL_CLKEN_CENT 0x28
47#define CLKEN_CPU (1 << 0)
48#define CLKEN_SRAM0 (1 << 1)
49#define CLKEN_SRAM1 (1 << 2)
50#define CLKEN_APB0 (1 << 3)
51#define CLKEN_APB1 (1 << 4)
52#define CLKEN_APB2 (1 << 5)
53#define K210_SYSCTL_CLKEN_PERI 0x2c
54#define CLKEN_ROM (1 << 0)
55#define CLKEN_DMA (1 << 1)
56#define CLKEN_AI (1 << 2)
57#define CLKEN_DVP (1 << 3)
58#define CLKEN_FFT (1 << 4)
59#define CLKEN_GPIO (1 << 5)
60#define CLKEN_SPI0 (1 << 6)
61#define CLKEN_SPI1 (1 << 7)
62#define CLKEN_SPI2 (1 << 8)
63#define CLKEN_SPI3 (1 << 9)
64#define CLKEN_I2S0 (1 << 10)
65#define CLKEN_I2S1 (1 << 11)
66#define CLKEN_I2S2 (1 << 12)
67#define CLKEN_I2C0 (1 << 13)
68#define CLKEN_I2C1 (1 << 14)
69#define CLKEN_I2C2 (1 << 15)
70#define CLKEN_UART1 (1 << 16)
71#define CLKEN_UART2 (1 << 17)
72#define CLKEN_UART3 (1 << 18)
73#define CLKEN_AES (1 << 19)
74#define CLKEN_FPIO (1 << 20)
75#define CLKEN_TIMER0 (1 << 21)
76#define CLKEN_TIMER1 (1 << 22)
77#define CLKEN_TIMER2 (1 << 23)
78#define CLKEN_WDT0 (1 << 24)
79#define CLKEN_WDT1 (1 << 25)
80#define CLKEN_SHA (1 << 26)
81#define CLKEN_OTP (1 << 27)
82#define CLKEN_RTC (1 << 29)
22/* Register bits */
23/* K210_SYSCTL_PLL1: clkr: 4bits, clkf1: 6bits, clkod: 4bits, bwadj: 4bits */
24#define PLL_RESET (1 << 20)
25#define PLL_PWR (1 << 21)
26#define PLL_BYPASS (1 << 23)
27#define PLL_OUT_EN (1 << 25)
28/* K210_SYSCTL_PLL_LOCK */
29#define PLL1_LOCK1 (1 << 8)
30#define PLL1_LOCK2 (1 << 9)
31#define PLL1_SLIP_CLEAR (1 << 10)
32/* K210_SYSCTL_SEL0 */
33#define CLKSEL_ACLK (1 << 0)
34/* K210_SYSCTL_CLKEN_CENT */
35#define CLKEN_CPU (1 << 0)
36#define CLKEN_SRAM0 (1 << 1)
37#define CLKEN_SRAM1 (1 << 2)
38/* K210_SYSCTL_EN_PERI */
39#define CLKEN_ROM (1 << 0)
40#define CLKEN_TIMER0 (1 << 21)
41#define CLKEN_RTC (1 << 29)
83
84struct k210_sysctl {
85 void __iomem *regs;
86 struct clk_hw hw;
87};
88
89static void k210_set_bits(u32 val, void __iomem *reg)
90{

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135 struct k210_sysctl *s = container_of(hw, struct k210_sysctl, hw);
136 u32 clksel0, pll0;
137 u64 pll0_freq, clkr0, clkf0, clkod0;
138
139 /*
140 * If the clock selector is not set, use the base frequency.
141 * Otherwise, use PLL0 frequency with a frequency divisor.
142 */
42
43struct k210_sysctl {
44 void __iomem *regs;
45 struct clk_hw hw;
46};
47
48static void k210_set_bits(u32 val, void __iomem *reg)
49{

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94 struct k210_sysctl *s = container_of(hw, struct k210_sysctl, hw);
95 u32 clksel0, pll0;
96 u64 pll0_freq, clkr0, clkf0, clkod0;
97
98 /*
99 * If the clock selector is not set, use the base frequency.
100 * Otherwise, use PLL0 frequency with a frequency divisor.
101 */
143 clksel0 = readl(s->regs + K210_SYSCTL_CLKSEL0);
102 clksel0 = readl(s->regs + K210_SYSCTL_SEL0);
144 if (!(clksel0 & CLKSEL_ACLK))
145 return K210_SYSCTL_CLK0_FREQ;
146
147 /*
148 * Get PLL0 frequency:
149 * freq = base frequency * clkf0 / (clkr0 * clkod0)
150 */
151 pll0 = readl(s->regs + K210_SYSCTL_PLL0);

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232 panic("K210 sysctl ioremap");
233
234 /* Enable PLL1 to make the KPU SRAM useable */
235 k210_pll1_enable(regs);
236
237 k210_set_bits(PLL_OUT_EN, regs + K210_SYSCTL_PLL0);
238
239 k210_set_bits(CLKEN_CPU | CLKEN_SRAM0 | CLKEN_SRAM1,
103 if (!(clksel0 & CLKSEL_ACLK))
104 return K210_SYSCTL_CLK0_FREQ;
105
106 /*
107 * Get PLL0 frequency:
108 * freq = base frequency * clkf0 / (clkr0 * clkod0)
109 */
110 pll0 = readl(s->regs + K210_SYSCTL_PLL0);

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191 panic("K210 sysctl ioremap");
192
193 /* Enable PLL1 to make the KPU SRAM useable */
194 k210_pll1_enable(regs);
195
196 k210_set_bits(PLL_OUT_EN, regs + K210_SYSCTL_PLL0);
197
198 k210_set_bits(CLKEN_CPU | CLKEN_SRAM0 | CLKEN_SRAM1,
240 regs + K210_SYSCTL_CLKEN_CENT);
199 regs + K210_SYSCTL_EN_CENT);
241 k210_set_bits(CLKEN_ROM | CLKEN_TIMER0 | CLKEN_RTC,
200 k210_set_bits(CLKEN_ROM | CLKEN_TIMER0 | CLKEN_RTC,
242 regs + K210_SYSCTL_CLKEN_PERI);
201 regs + K210_SYSCTL_EN_PERI);
243
202
244 k210_set_bits(CLKSEL_ACLK, regs + K210_SYSCTL_CLKSEL0);
203 k210_set_bits(CLKSEL_ACLK, regs + K210_SYSCTL_SEL0);
245
246 iounmap(regs);
247}
248SOC_EARLY_INIT_DECLARE(generic_k210, "kendryte,k210", k210_soc_early_init);
204
205 iounmap(regs);
206}
207SOC_EARLY_INIT_DECLARE(generic_k210, "kendryte,k210", k210_soc_early_init);