ql4_nx.c (0b6c404a07e3240b95aa5682fb8fd57c41609d7a) ql4_nx.c (f8086f4fd462195a5a824c851997bd12ffceae00)
1/*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7#include <linux/delay.h>
8#include <linux/io.h>

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46#define MAX_CRB_XFORM 60
47static unsigned long crb_addr_xform[MAX_CRB_XFORM];
48static int qla4_8xxx_crb_table_initialized;
49
50#define qla4_8xxx_crb_addr_transform(name) \
51 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
52 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
53static void
1/*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7#include <linux/delay.h>
8#include <linux/io.h>

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46#define MAX_CRB_XFORM 60
47static unsigned long crb_addr_xform[MAX_CRB_XFORM];
48static int qla4_8xxx_crb_table_initialized;
49
50#define qla4_8xxx_crb_addr_transform(name) \
51 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
52 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
53static void
54qla4_8xxx_crb_addr_transform_setup(void)
54qla4_82xx_crb_addr_transform_setup(void)
55{
56 qla4_8xxx_crb_addr_transform(XDMA);
57 qla4_8xxx_crb_addr_transform(TIMR);
58 qla4_8xxx_crb_addr_transform(SRE);
59 qla4_8xxx_crb_addr_transform(SQN3);
60 qla4_8xxx_crb_addr_transform(SQN2);
61 qla4_8xxx_crb_addr_transform(SQN1);
62 qla4_8xxx_crb_addr_transform(SQN0);

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348};
349
350/*
351 * In: 'off' is offset from CRB space in 128M pci map
352 * Out: 'off' is 2M pci map addr
353 * side effect: lock crb window
354 */
355static void
55{
56 qla4_8xxx_crb_addr_transform(XDMA);
57 qla4_8xxx_crb_addr_transform(TIMR);
58 qla4_8xxx_crb_addr_transform(SRE);
59 qla4_8xxx_crb_addr_transform(SQN3);
60 qla4_8xxx_crb_addr_transform(SQN2);
61 qla4_8xxx_crb_addr_transform(SQN1);
62 qla4_8xxx_crb_addr_transform(SQN0);

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348};
349
350/*
351 * In: 'off' is offset from CRB space in 128M pci map
352 * Out: 'off' is 2M pci map addr
353 * side effect: lock crb window
354 */
355static void
356qla4_8xxx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
356qla4_82xx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off)
357{
358 u32 win_read;
359
360 ha->crb_win = CRB_HI(*off);
361 writel(ha->crb_win,
362 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
363
364 /* Read back value to make sure write has gone through before trying
365 * to use it. */
366 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
367 if (win_read != ha->crb_win) {
368 DEBUG2(ql4_printk(KERN_INFO, ha,
369 "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
370 " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
371 }
372 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
373}
374
375void
357{
358 u32 win_read;
359
360 ha->crb_win = CRB_HI(*off);
361 writel(ha->crb_win,
362 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
363
364 /* Read back value to make sure write has gone through before trying
365 * to use it. */
366 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase));
367 if (win_read != ha->crb_win) {
368 DEBUG2(ql4_printk(KERN_INFO, ha,
369 "%s: Written crbwin (0x%x) != Read crbwin (0x%x),"
370 " off=0x%lx\n", __func__, ha->crb_win, win_read, *off));
371 }
372 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
373}
374
375void
376qla4_8xxx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
376qla4_82xx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data)
377{
378 unsigned long flags = 0;
379 int rv;
380
377{
378 unsigned long flags = 0;
379 int rv;
380
381 rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off);
381 rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
382
383 BUG_ON(rv == -1);
384
385 if (rv == 1) {
386 write_lock_irqsave(&ha->hw_lock, flags);
382
383 BUG_ON(rv == -1);
384
385 if (rv == 1) {
386 write_lock_irqsave(&ha->hw_lock, flags);
387 qla4_8xxx_crb_win_lock(ha);
388 qla4_8xxx_pci_set_crbwindow_2M(ha, &off);
387 qla4_82xx_crb_win_lock(ha);
388 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
389 }
390
391 writel(data, (void __iomem *)off);
392
393 if (rv == 1) {
389 }
390
391 writel(data, (void __iomem *)off);
392
393 if (rv == 1) {
394 qla4_8xxx_crb_win_unlock(ha);
394 qla4_82xx_crb_win_unlock(ha);
395 write_unlock_irqrestore(&ha->hw_lock, flags);
396 }
397}
398
399int
395 write_unlock_irqrestore(&ha->hw_lock, flags);
396 }
397}
398
399int
400qla4_8xxx_rd_32(struct scsi_qla_host *ha, ulong off)
400qla4_82xx_rd_32(struct scsi_qla_host *ha, ulong off)
401{
402 unsigned long flags = 0;
403 int rv;
404 u32 data;
405
401{
402 unsigned long flags = 0;
403 int rv;
404 u32 data;
405
406 rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off);
406 rv = qla4_82xx_pci_get_crb_addr_2M(ha, &off);
407
408 BUG_ON(rv == -1);
409
410 if (rv == 1) {
411 write_lock_irqsave(&ha->hw_lock, flags);
407
408 BUG_ON(rv == -1);
409
410 if (rv == 1) {
411 write_lock_irqsave(&ha->hw_lock, flags);
412 qla4_8xxx_crb_win_lock(ha);
413 qla4_8xxx_pci_set_crbwindow_2M(ha, &off);
412 qla4_82xx_crb_win_lock(ha);
413 qla4_82xx_pci_set_crbwindow_2M(ha, &off);
414 }
415 data = readl((void __iomem *)off);
416
417 if (rv == 1) {
414 }
415 data = readl((void __iomem *)off);
416
417 if (rv == 1) {
418 qla4_8xxx_crb_win_unlock(ha);
418 qla4_82xx_crb_win_unlock(ha);
419 write_unlock_irqrestore(&ha->hw_lock, flags);
420 }
421 return data;
422}
423
424/* Minidump related functions */
425static int qla4_8xxx_md_rw_32(struct scsi_qla_host *ha, uint32_t off,
426 u32 data, uint8_t flag)

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450 rval = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
451 ha->nx_pcibase));
452
453 return rval;
454}
455
456#define CRB_WIN_LOCK_TIMEOUT 100000000
457
419 write_unlock_irqrestore(&ha->hw_lock, flags);
420 }
421 return data;
422}
423
424/* Minidump related functions */
425static int qla4_8xxx_md_rw_32(struct scsi_qla_host *ha, uint32_t off,
426 u32 data, uint8_t flag)

--- 23 unchanged lines hidden (view full) ---

450 rval = readl((void __iomem *)(off_value + CRB_INDIRECT_2M +
451 ha->nx_pcibase));
452
453 return rval;
454}
455
456#define CRB_WIN_LOCK_TIMEOUT 100000000
457
458int qla4_8xxx_crb_win_lock(struct scsi_qla_host *ha)
458int qla4_82xx_crb_win_lock(struct scsi_qla_host *ha)
459{
460 int i;
461 int done = 0, timeout = 0;
462
463 while (!done) {
464 /* acquire semaphore3 from PCI HW block */
459{
460 int i;
461 int done = 0, timeout = 0;
462
463 while (!done) {
464 /* acquire semaphore3 from PCI HW block */
465 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
465 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
466 if (done == 1)
467 break;
468 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
469 return -1;
470
471 timeout++;
472
473 /* Yield CPU */
474 if (!in_interrupt())
475 schedule();
476 else {
477 for (i = 0; i < 20; i++)
478 cpu_relax(); /*This a nop instr on i386*/
479 }
480 }
466 if (done == 1)
467 break;
468 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
469 return -1;
470
471 timeout++;
472
473 /* Yield CPU */
474 if (!in_interrupt())
475 schedule();
476 else {
477 for (i = 0; i < 20; i++)
478 cpu_relax(); /*This a nop instr on i386*/
479 }
480 }
481 qla4_8xxx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
481 qla4_82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num);
482 return 0;
483}
484
482 return 0;
483}
484
485void qla4_8xxx_crb_win_unlock(struct scsi_qla_host *ha)
485void qla4_82xx_crb_win_unlock(struct scsi_qla_host *ha)
486{
486{
487 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
487 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
488}
489
490#define IDC_LOCK_TIMEOUT 100000000
491
492/**
488}
489
490#define IDC_LOCK_TIMEOUT 100000000
491
492/**
493 * qla4_8xxx_idc_lock - hw_lock
493 * qla4_82xx_idc_lock - hw_lock
494 * @ha: pointer to adapter structure
495 *
496 * General purpose lock used to synchronize access to
497 * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
498 **/
494 * @ha: pointer to adapter structure
495 *
496 * General purpose lock used to synchronize access to
497 * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc.
498 **/
499int qla4_8xxx_idc_lock(struct scsi_qla_host *ha)
499int qla4_82xx_idc_lock(struct scsi_qla_host *ha)
500{
501 int i;
502 int done = 0, timeout = 0;
503
504 while (!done) {
505 /* acquire semaphore5 from PCI HW block */
500{
501 int i;
502 int done = 0, timeout = 0;
503
504 while (!done) {
505 /* acquire semaphore5 from PCI HW block */
506 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
506 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
507 if (done == 1)
508 break;
509 if (timeout >= IDC_LOCK_TIMEOUT)
510 return -1;
511
512 timeout++;
513
514 /* Yield CPU */
515 if (!in_interrupt())
516 schedule();
517 else {
518 for (i = 0; i < 20; i++)
519 cpu_relax(); /*This a nop instr on i386*/
520 }
521 }
522 return 0;
523}
524
507 if (done == 1)
508 break;
509 if (timeout >= IDC_LOCK_TIMEOUT)
510 return -1;
511
512 timeout++;
513
514 /* Yield CPU */
515 if (!in_interrupt())
516 schedule();
517 else {
518 for (i = 0; i < 20; i++)
519 cpu_relax(); /*This a nop instr on i386*/
520 }
521 }
522 return 0;
523}
524
525void qla4_8xxx_idc_unlock(struct scsi_qla_host *ha)
525void qla4_82xx_idc_unlock(struct scsi_qla_host *ha)
526{
526{
527 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
527 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
528}
529
530int
528}
529
530int
531qla4_8xxx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
531qla4_82xx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off)
532{
533 struct crb_128M_2M_sub_block_map *m;
534
535 if (*off >= QLA82XX_CRB_MAX)
536 return -1;
537
538 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
539 *off = (*off - QLA82XX_PCI_CAMQM) +

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566#define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
567 (((addr) <= (high)) && ((addr) >= (low)))
568
569/*
570* check memory access boundary.
571* used by test agent. support ddr access only for now
572*/
573static unsigned long
532{
533 struct crb_128M_2M_sub_block_map *m;
534
535 if (*off >= QLA82XX_CRB_MAX)
536 return -1;
537
538 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) {
539 *off = (*off - QLA82XX_PCI_CAMQM) +

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566#define QLA82XX_ADDR_IN_RANGE(addr, low, high) \
567 (((addr) <= (high)) && ((addr) >= (low)))
568
569/*
570* check memory access boundary.
571* used by test agent. support ddr access only for now
572*/
573static unsigned long
574qla4_8xxx_pci_mem_bound_check(struct scsi_qla_host *ha,
574qla4_82xx_pci_mem_bound_check(struct scsi_qla_host *ha,
575 unsigned long long addr, int size)
576{
577 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
578 QLA82XX_ADDR_DDR_NET_MAX) ||
579 !QLA82XX_ADDR_IN_RANGE(addr + size - 1,
580 QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) ||
581 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
582 return 0;
583 }
584 return 1;
585}
586
587static int qla4_8xxx_pci_set_window_warning_count;
588
589static unsigned long
575 unsigned long long addr, int size)
576{
577 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
578 QLA82XX_ADDR_DDR_NET_MAX) ||
579 !QLA82XX_ADDR_IN_RANGE(addr + size - 1,
580 QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) ||
581 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
582 return 0;
583 }
584 return 1;
585}
586
587static int qla4_8xxx_pci_set_window_warning_count;
588
589static unsigned long
590qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
590qla4_82xx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr)
591{
592 int window;
593 u32 win_read;
594
595 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
596 QLA82XX_ADDR_DDR_NET_MAX)) {
597 /* DDR network side */
598 window = MN_WIN(addr);
599 ha->ddr_mn_window = window;
591{
592 int window;
593 u32 win_read;
594
595 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,
596 QLA82XX_ADDR_DDR_NET_MAX)) {
597 /* DDR network side */
598 window = MN_WIN(addr);
599 ha->ddr_mn_window = window;
600 qla4_8xxx_wr_32(ha, ha->mn_win_crb |
600 qla4_82xx_wr_32(ha, ha->mn_win_crb |
601 QLA82XX_PCI_CRBSPACE, window);
601 QLA82XX_PCI_CRBSPACE, window);
602 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb |
602 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
603 QLA82XX_PCI_CRBSPACE);
604 if ((win_read << 17) != window) {
605 ql4_printk(KERN_WARNING, ha,
606 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
607 __func__, window, win_read);
608 }
609 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
610 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
611 QLA82XX_ADDR_OCM0_MAX)) {
612 unsigned int temp1;
613 /* if bits 19:18&17:11 are on */
614 if ((addr & 0x00ff800) == 0xff800) {
615 printk("%s: QM access not handled.\n", __func__);
616 addr = -1UL;
617 }
618
619 window = OCM_WIN(addr);
620 ha->ddr_mn_window = window;
603 QLA82XX_PCI_CRBSPACE);
604 if ((win_read << 17) != window) {
605 ql4_printk(KERN_WARNING, ha,
606 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n",
607 __func__, window, win_read);
608 }
609 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
610 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0,
611 QLA82XX_ADDR_OCM0_MAX)) {
612 unsigned int temp1;
613 /* if bits 19:18&17:11 are on */
614 if ((addr & 0x00ff800) == 0xff800) {
615 printk("%s: QM access not handled.\n", __func__);
616 addr = -1UL;
617 }
618
619 window = OCM_WIN(addr);
620 ha->ddr_mn_window = window;
621 qla4_8xxx_wr_32(ha, ha->mn_win_crb |
621 qla4_82xx_wr_32(ha, ha->mn_win_crb |
622 QLA82XX_PCI_CRBSPACE, window);
622 QLA82XX_PCI_CRBSPACE, window);
623 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb |
623 win_read = qla4_82xx_rd_32(ha, ha->mn_win_crb |
624 QLA82XX_PCI_CRBSPACE);
625 temp1 = ((window & 0x1FF) << 7) |
626 ((window & 0x0FFFE0000) >> 17);
627 if (win_read != temp1) {
628 printk("%s: Written OCMwin (0x%x) != Read"
629 " OCMwin (0x%x)\n", __func__, temp1, win_read);
630 }
631 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
632
633 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
634 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
635 /* QDR network side */
636 window = MS_WIN(addr);
637 ha->qdr_sn_window = window;
624 QLA82XX_PCI_CRBSPACE);
625 temp1 = ((window & 0x1FF) << 7) |
626 ((window & 0x0FFFE0000) >> 17);
627 if (win_read != temp1) {
628 printk("%s: Written OCMwin (0x%x) != Read"
629 " OCMwin (0x%x)\n", __func__, temp1, win_read);
630 }
631 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
632
633 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET,
634 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
635 /* QDR network side */
636 window = MS_WIN(addr);
637 ha->qdr_sn_window = window;
638 qla4_8xxx_wr_32(ha, ha->ms_win_crb |
638 qla4_82xx_wr_32(ha, ha->ms_win_crb |
639 QLA82XX_PCI_CRBSPACE, window);
639 QLA82XX_PCI_CRBSPACE, window);
640 win_read = qla4_8xxx_rd_32(ha,
640 win_read = qla4_82xx_rd_32(ha,
641 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
642 if (win_read != window) {
643 printk("%s: Written MSwin (0x%x) != Read "
644 "MSwin (0x%x)\n", __func__, window, win_read);
645 }
646 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
647
648 } else {

--- 7 unchanged lines hidden (view full) ---

656 __func__, DRIVER_NAME);
657 }
658 addr = -1UL;
659 }
660 return addr;
661}
662
663/* check if address is in the same windows as the previous access */
641 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
642 if (win_read != window) {
643 printk("%s: Written MSwin (0x%x) != Read "
644 "MSwin (0x%x)\n", __func__, window, win_read);
645 }
646 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
647
648 } else {

--- 7 unchanged lines hidden (view full) ---

656 __func__, DRIVER_NAME);
657 }
658 addr = -1UL;
659 }
660 return addr;
661}
662
663/* check if address is in the same windows as the previous access */
664static int qla4_8xxx_pci_is_same_window(struct scsi_qla_host *ha,
664static int qla4_82xx_pci_is_same_window(struct scsi_qla_host *ha,
665 unsigned long long addr)
666{
667 int window;
668 unsigned long long qdr_max;
669
670 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
671
672 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,

--- 12 unchanged lines hidden (view full) ---

685 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
686 if (ha->qdr_sn_window == window)
687 return 1;
688 }
689
690 return 0;
691}
692
665 unsigned long long addr)
666{
667 int window;
668 unsigned long long qdr_max;
669
670 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
671
672 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET,

--- 12 unchanged lines hidden (view full) ---

685 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
686 if (ha->qdr_sn_window == window)
687 return 1;
688 }
689
690 return 0;
691}
692
693static int qla4_8xxx_pci_mem_read_direct(struct scsi_qla_host *ha,
693static int qla4_82xx_pci_mem_read_direct(struct scsi_qla_host *ha,
694 u64 off, void *data, int size)
695{
696 unsigned long flags;
697 void __iomem *addr;
698 int ret = 0;
699 u64 start;
700 void __iomem *mem_ptr = NULL;
701 unsigned long mem_base;
702 unsigned long mem_page;
703
704 write_lock_irqsave(&ha->hw_lock, flags);
705
706 /*
707 * If attempting to access unknown address or straddle hw windows,
708 * do not access.
709 */
694 u64 off, void *data, int size)
695{
696 unsigned long flags;
697 void __iomem *addr;
698 int ret = 0;
699 u64 start;
700 void __iomem *mem_ptr = NULL;
701 unsigned long mem_base;
702 unsigned long mem_page;
703
704 write_lock_irqsave(&ha->hw_lock, flags);
705
706 /*
707 * If attempting to access unknown address or straddle hw windows,
708 * do not access.
709 */
710 start = qla4_8xxx_pci_set_window(ha, off);
710 start = qla4_82xx_pci_set_window(ha, off);
711 if ((start == -1UL) ||
711 if ((start == -1UL) ||
712 (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) {
712 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
713 write_unlock_irqrestore(&ha->hw_lock, flags);
714 printk(KERN_ERR"%s out of bound pci memory access. "
715 "offset is 0x%llx\n", DRIVER_NAME, off);
716 return -1;
717 }
718
719 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
720 if (!addr) {

--- 37 unchanged lines hidden (view full) ---

758 write_unlock_irqrestore(&ha->hw_lock, flags);
759
760 if (mem_ptr)
761 iounmap(mem_ptr);
762 return ret;
763}
764
765static int
713 write_unlock_irqrestore(&ha->hw_lock, flags);
714 printk(KERN_ERR"%s out of bound pci memory access. "
715 "offset is 0x%llx\n", DRIVER_NAME, off);
716 return -1;
717 }
718
719 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
720 if (!addr) {

--- 37 unchanged lines hidden (view full) ---

758 write_unlock_irqrestore(&ha->hw_lock, flags);
759
760 if (mem_ptr)
761 iounmap(mem_ptr);
762 return ret;
763}
764
765static int
766qla4_8xxx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
766qla4_82xx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off,
767 void *data, int size)
768{
769 unsigned long flags;
770 void __iomem *addr;
771 int ret = 0;
772 u64 start;
773 void __iomem *mem_ptr = NULL;
774 unsigned long mem_base;
775 unsigned long mem_page;
776
777 write_lock_irqsave(&ha->hw_lock, flags);
778
779 /*
780 * If attempting to access unknown address or straddle hw windows,
781 * do not access.
782 */
767 void *data, int size)
768{
769 unsigned long flags;
770 void __iomem *addr;
771 int ret = 0;
772 u64 start;
773 void __iomem *mem_ptr = NULL;
774 unsigned long mem_base;
775 unsigned long mem_page;
776
777 write_lock_irqsave(&ha->hw_lock, flags);
778
779 /*
780 * If attempting to access unknown address or straddle hw windows,
781 * do not access.
782 */
783 start = qla4_8xxx_pci_set_window(ha, off);
783 start = qla4_82xx_pci_set_window(ha, off);
784 if ((start == -1UL) ||
784 if ((start == -1UL) ||
785 (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) {
785 (qla4_82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
786 write_unlock_irqrestore(&ha->hw_lock, flags);
787 printk(KERN_ERR"%s out of bound pci memory access. "
788 "offset is 0x%llx\n", DRIVER_NAME, off);
789 return -1;
790 }
791
792 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
793 if (!addr) {

--- 36 unchanged lines hidden (view full) ---

830 if (mem_ptr)
831 iounmap(mem_ptr);
832 return ret;
833}
834
835#define MTU_FUDGE_FACTOR 100
836
837static unsigned long
786 write_unlock_irqrestore(&ha->hw_lock, flags);
787 printk(KERN_ERR"%s out of bound pci memory access. "
788 "offset is 0x%llx\n", DRIVER_NAME, off);
789 return -1;
790 }
791
792 addr = qla4_8xxx_pci_base_offsetfset(ha, start);
793 if (!addr) {

--- 36 unchanged lines hidden (view full) ---

830 if (mem_ptr)
831 iounmap(mem_ptr);
832 return ret;
833}
834
835#define MTU_FUDGE_FACTOR 100
836
837static unsigned long
838qla4_8xxx_decode_crb_addr(unsigned long addr)
838qla4_82xx_decode_crb_addr(unsigned long addr)
839{
840 int i;
841 unsigned long base_addr, offset, pci_base;
842
843 if (!qla4_8xxx_crb_table_initialized)
839{
840 int i;
841 unsigned long base_addr, offset, pci_base;
842
843 if (!qla4_8xxx_crb_table_initialized)
844 qla4_8xxx_crb_addr_transform_setup();
844 qla4_82xx_crb_addr_transform_setup();
845
846 pci_base = ADDR_ERROR;
847 base_addr = addr & 0xfff00000;
848 offset = addr & 0x000fffff;
849
850 for (i = 0; i < MAX_CRB_XFORM; i++) {
851 if (crb_addr_xform[i] == base_addr) {
852 pci_base = i << 20;

--- 5 unchanged lines hidden (view full) ---

858 else
859 return pci_base + offset;
860}
861
862static long rom_max_timeout = 100;
863static long qla4_8xxx_rom_lock_timeout = 100;
864
865static int
845
846 pci_base = ADDR_ERROR;
847 base_addr = addr & 0xfff00000;
848 offset = addr & 0x000fffff;
849
850 for (i = 0; i < MAX_CRB_XFORM; i++) {
851 if (crb_addr_xform[i] == base_addr) {
852 pci_base = i << 20;

--- 5 unchanged lines hidden (view full) ---

858 else
859 return pci_base + offset;
860}
861
862static long rom_max_timeout = 100;
863static long qla4_8xxx_rom_lock_timeout = 100;
864
865static int
866qla4_8xxx_rom_lock(struct scsi_qla_host *ha)
866qla4_82xx_rom_lock(struct scsi_qla_host *ha)
867{
868 int i;
869 int done = 0, timeout = 0;
870
871 while (!done) {
872 /* acquire semaphore2 from PCI HW block */
873
867{
868 int i;
869 int done = 0, timeout = 0;
870
871 while (!done) {
872 /* acquire semaphore2 from PCI HW block */
873
874 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
874 done = qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
875 if (done == 1)
876 break;
877 if (timeout >= qla4_8xxx_rom_lock_timeout)
878 return -1;
879
880 timeout++;
881
882 /* Yield CPU */
883 if (!in_interrupt())
884 schedule();
885 else {
886 for (i = 0; i < 20; i++)
887 cpu_relax(); /*This a nop instr on i386*/
888 }
889 }
875 if (done == 1)
876 break;
877 if (timeout >= qla4_8xxx_rom_lock_timeout)
878 return -1;
879
880 timeout++;
881
882 /* Yield CPU */
883 if (!in_interrupt())
884 schedule();
885 else {
886 for (i = 0; i < 20; i++)
887 cpu_relax(); /*This a nop instr on i386*/
888 }
889 }
890 qla4_8xxx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
890 qla4_82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER);
891 return 0;
892}
893
894static void
891 return 0;
892}
893
894static void
895qla4_8xxx_rom_unlock(struct scsi_qla_host *ha)
895qla4_82xx_rom_unlock(struct scsi_qla_host *ha)
896{
896{
897 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
897 qla4_82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
898}
899
900static int
898}
899
900static int
901qla4_8xxx_wait_rom_done(struct scsi_qla_host *ha)
901qla4_82xx_wait_rom_done(struct scsi_qla_host *ha)
902{
903 long timeout = 0;
904 long done = 0 ;
905
906 while (done == 0) {
902{
903 long timeout = 0;
904 long done = 0 ;
905
906 while (done == 0) {
907 done = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
907 done = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
908 done &= 2;
909 timeout++;
910 if (timeout >= rom_max_timeout) {
911 printk("%s: Timeout reached waiting for rom done",
912 DRIVER_NAME);
913 return -1;
914 }
915 }
916 return 0;
917}
918
919static int
908 done &= 2;
909 timeout++;
910 if (timeout >= rom_max_timeout) {
911 printk("%s: Timeout reached waiting for rom done",
912 DRIVER_NAME);
913 return -1;
914 }
915 }
916 return 0;
917}
918
919static int
920qla4_8xxx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
920qla4_82xx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
921{
921{
922 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
923 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
924 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
925 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
926 if (qla4_8xxx_wait_rom_done(ha)) {
922 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
923 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
924 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
925 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb);
926 if (qla4_82xx_wait_rom_done(ha)) {
927 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
928 return -1;
929 }
930 /* reset abyte_cnt and dummy_byte_cnt */
927 printk("%s: Error waiting for rom done\n", DRIVER_NAME);
928 return -1;
929 }
930 /* reset abyte_cnt and dummy_byte_cnt */
931 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
931 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
932 udelay(10);
932 udelay(10);
933 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
933 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
934
934
935 *valp = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
935 *valp = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
936 return 0;
937}
938
939static int
936 return 0;
937}
938
939static int
940qla4_8xxx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
940qla4_82xx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp)
941{
942 int ret, loops = 0;
943
941{
942 int ret, loops = 0;
943
944 while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) {
944 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
945 udelay(100);
946 loops++;
947 }
948 if (loops >= 50000) {
945 udelay(100);
946 loops++;
947 }
948 if (loops >= 50000) {
949 printk("%s: qla4_8xxx_rom_lock failed\n", DRIVER_NAME);
949 ql4_printk(KERN_WARNING, ha, "%s: qla4_82xx_rom_lock failed\n",
950 DRIVER_NAME);
950 return -1;
951 }
951 return -1;
952 }
952 ret = qla4_8xxx_do_rom_fast_read(ha, addr, valp);
953 qla4_8xxx_rom_unlock(ha);
953 ret = qla4_82xx_do_rom_fast_read(ha, addr, valp);
954 qla4_82xx_rom_unlock(ha);
954 return ret;
955}
956
957/**
958 * This routine does CRB initialize sequence
959 * to put the ISP into operational state
960 **/
961static int
955 return ret;
956}
957
958/**
959 * This routine does CRB initialize sequence
960 * to put the ISP into operational state
961 **/
962static int
962qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
963qla4_82xx_pinit_from_rom(struct scsi_qla_host *ha, int verbose)
963{
964 int addr, val;
965 int i ;
966 struct crb_addr_pair *buf;
967 unsigned long off;
968 unsigned offset, n;
969
970 struct crb_addr_pair {
971 long addr;
972 long data;
973 };
974
975 /* Halt all the indiviual PEGs and other blocks of the ISP */
964{
965 int addr, val;
966 int i ;
967 struct crb_addr_pair *buf;
968 unsigned long off;
969 unsigned offset, n;
970
971 struct crb_addr_pair {
972 long addr;
973 long data;
974 };
975
976 /* Halt all the indiviual PEGs and other blocks of the ISP */
976 qla4_8xxx_rom_lock(ha);
977 qla4_82xx_rom_lock(ha);
977
978 /* disable all I2Q */
978
979 /* disable all I2Q */
979 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
980 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
981 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
982 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
983 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
984 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
980 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
981 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
982 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
983 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
984 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
985 qla4_82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
985
986 /* disable all niu interrupts */
986
987 /* disable all niu interrupts */
987 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
988 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
988 /* disable xge rx/tx */
989 /* disable xge rx/tx */
989 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
990 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
990 /* disable xg1 rx/tx */
991 /* disable xg1 rx/tx */
991 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
992 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
992 /* disable sideband mac */
993 /* disable sideband mac */
993 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
994 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
994 /* disable ap0 mac */
995 /* disable ap0 mac */
995 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
996 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
996 /* disable ap1 mac */
997 /* disable ap1 mac */
997 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
998 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
998
999 /* halt sre */
999
1000 /* halt sre */
1000 val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1001 qla4_8xxx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1001 val = qla4_82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1002 qla4_82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1002
1003 /* halt epg */
1003
1004 /* halt epg */
1004 qla4_8xxx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1005 qla4_82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1005
1006 /* halt timers */
1006
1007 /* halt timers */
1007 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1008 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1009 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1010 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1011 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1012 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1008 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1009 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1010 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1011 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1012 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1013 qla4_82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1013
1014 /* halt pegs */
1014
1015 /* halt pegs */
1015 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1016 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1017 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1018 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1019 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1016 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1017 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1018 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1019 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1020 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1020 msleep(5);
1021
1022 /* big hammer */
1023 if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
1024 /* don't reset CAM block on reset */
1021 msleep(5);
1022
1023 /* big hammer */
1024 if (test_bit(DPC_RESET_HA, &ha->dpc_flags))
1025 /* don't reset CAM block on reset */
1025 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1026 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1026 else
1027 else
1027 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1028 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1028
1029
1029 qla4_8xxx_rom_unlock(ha);
1030 qla4_82xx_rom_unlock(ha);
1030
1031 /* Read the signature value from the flash.
1032 * Offset 0: Contain signature (0xcafecafe)
1033 * Offset 4: Offset and number of addr/value pairs
1034 * that present in CRB initialize sequence
1035 */
1031
1032 /* Read the signature value from the flash.
1033 * Offset 0: Contain signature (0xcafecafe)
1034 * Offset 4: Offset and number of addr/value pairs
1035 * that present in CRB initialize sequence
1036 */
1036 if (qla4_8xxx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1037 qla4_8xxx_rom_fast_read(ha, 4, &n) != 0) {
1037 if (qla4_82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1038 qla4_82xx_rom_fast_read(ha, 4, &n) != 0) {
1038 ql4_printk(KERN_WARNING, ha,
1039 "[ERROR] Reading crb_init area: n: %08x\n", n);
1040 return -1;
1041 }
1042
1043 /* Offset in flash = lower 16 bits
1044 * Number of enteries = upper 16 bits
1045 */

--- 14 unchanged lines hidden (view full) ---

1060 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1061 if (buf == NULL) {
1062 ql4_printk(KERN_WARNING, ha,
1063 "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
1064 return -1;
1065 }
1066
1067 for (i = 0; i < n; i++) {
1039 ql4_printk(KERN_WARNING, ha,
1040 "[ERROR] Reading crb_init area: n: %08x\n", n);
1041 return -1;
1042 }
1043
1044 /* Offset in flash = lower 16 bits
1045 * Number of enteries = upper 16 bits
1046 */

--- 14 unchanged lines hidden (view full) ---

1061 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL);
1062 if (buf == NULL) {
1063 ql4_printk(KERN_WARNING, ha,
1064 "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME);
1065 return -1;
1066 }
1067
1068 for (i = 0; i < n; i++) {
1068 if (qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1069 qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
1069 if (qla4_82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1070 qla4_82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) !=
1070 0) {
1071 kfree(buf);
1072 return -1;
1073 }
1074
1075 buf[i].addr = addr;
1076 buf[i].data = val;
1077 }
1078
1079 for (i = 0; i < n; i++) {
1080 /* Translate internal CRB initialization
1081 * address to PCI bus address
1082 */
1071 0) {
1072 kfree(buf);
1073 return -1;
1074 }
1075
1076 buf[i].addr = addr;
1077 buf[i].data = val;
1078 }
1079
1080 for (i = 0; i < n; i++) {
1081 /* Translate internal CRB initialization
1082 * address to PCI bus address
1083 */
1083 off = qla4_8xxx_decode_crb_addr((unsigned long)buf[i].addr) +
1084 off = qla4_82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1084 QLA82XX_PCI_CRBSPACE;
1085 /* Not all CRB addr/value pair to be written,
1086 * some of them are skipped
1087 */
1088
1089 /* skip if LS bit is set*/
1090 if (off & 0x1) {
1091 DEBUG2(ql4_printk(KERN_WARNING, ha,

--- 28 unchanged lines hidden (view full) ---

1120
1121 if (off == ADDR_ERROR) {
1122 ql4_printk(KERN_WARNING, ha,
1123 "%s: [ERROR] Unknown addr: 0x%08lx\n",
1124 DRIVER_NAME, buf[i].addr);
1125 continue;
1126 }
1127
1085 QLA82XX_PCI_CRBSPACE;
1086 /* Not all CRB addr/value pair to be written,
1087 * some of them are skipped
1088 */
1089
1090 /* skip if LS bit is set*/
1091 if (off & 0x1) {
1092 DEBUG2(ql4_printk(KERN_WARNING, ha,

--- 28 unchanged lines hidden (view full) ---

1121
1122 if (off == ADDR_ERROR) {
1123 ql4_printk(KERN_WARNING, ha,
1124 "%s: [ERROR] Unknown addr: 0x%08lx\n",
1125 DRIVER_NAME, buf[i].addr);
1126 continue;
1127 }
1128
1128 qla4_8xxx_wr_32(ha, off, buf[i].data);
1129 qla4_82xx_wr_32(ha, off, buf[i].data);
1129
1130 /* ISP requires much bigger delay to settle down,
1131 * else crb_window returns 0xffffffff
1132 */
1133 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1134 msleep(1000);
1135
1136 /* ISP requires millisec delay between
1137 * successive CRB register updation
1138 */
1139 msleep(1);
1140 }
1141
1142 kfree(buf);
1143
1144 /* Resetting the data and instruction cache */
1130
1131 /* ISP requires much bigger delay to settle down,
1132 * else crb_window returns 0xffffffff
1133 */
1134 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1135 msleep(1000);
1136
1137 /* ISP requires millisec delay between
1138 * successive CRB register updation
1139 */
1140 msleep(1);
1141 }
1142
1143 kfree(buf);
1144
1145 /* Resetting the data and instruction cache */
1145 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1146 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1147 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1146 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1147 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1148 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1148
1149 /* Clear all protocol processing engines */
1149
1150 /* Clear all protocol processing engines */
1150 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1151 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1152 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1153 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1154 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1155 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1156 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1157 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1151 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1152 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1153 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1154 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1155 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1156 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1157 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1158 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1158
1159 return 0;
1160}
1161
1162static int
1159
1160 return 0;
1161}
1162
1163static int
1163qla4_8xxx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1164qla4_82xx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start)
1164{
1165 int i, rval = 0;
1166 long size = 0;
1167 long flashaddr, memaddr;
1168 u64 data;
1169 u32 high, low;
1170
1171 flashaddr = memaddr = ha->hw.flt_region_bootload;
1172 size = (image_start - flashaddr) / 8;
1173
1174 DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1175 ha->host_no, __func__, flashaddr, image_start));
1176
1177 for (i = 0; i < size; i++) {
1165{
1166 int i, rval = 0;
1167 long size = 0;
1168 long flashaddr, memaddr;
1169 u64 data;
1170 u32 high, low;
1171
1172 flashaddr = memaddr = ha->hw.flt_region_bootload;
1173 size = (image_start - flashaddr) / 8;
1174
1175 DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n",
1176 ha->host_no, __func__, flashaddr, image_start));
1177
1178 for (i = 0; i < size; i++) {
1178 if ((qla4_8xxx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1179 (qla4_8xxx_rom_fast_read(ha, flashaddr + 4,
1179 if ((qla4_82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1180 (qla4_82xx_rom_fast_read(ha, flashaddr + 4,
1180 (int *)&high))) {
1181 rval = -1;
1182 goto exit_load_from_flash;
1183 }
1184 data = ((u64)high << 32) | low ;
1181 (int *)&high))) {
1182 rval = -1;
1183 goto exit_load_from_flash;
1184 }
1185 data = ((u64)high << 32) | low ;
1185 rval = qla4_8xxx_pci_mem_write_2M(ha, memaddr, &data, 8);
1186 rval = qla4_82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1186 if (rval)
1187 goto exit_load_from_flash;
1188
1189 flashaddr += 8;
1190 memaddr += 8;
1191
1192 if (i % 0x1000 == 0)
1193 msleep(1);
1194
1195 }
1196
1197 udelay(100);
1198
1199 read_lock(&ha->hw_lock);
1187 if (rval)
1188 goto exit_load_from_flash;
1189
1190 flashaddr += 8;
1191 memaddr += 8;
1192
1193 if (i % 0x1000 == 0)
1194 msleep(1);
1195
1196 }
1197
1198 udelay(100);
1199
1200 read_lock(&ha->hw_lock);
1200 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1201 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1201 qla4_82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1202 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1202 read_unlock(&ha->hw_lock);
1203
1204exit_load_from_flash:
1205 return rval;
1206}
1207
1203 read_unlock(&ha->hw_lock);
1204
1205exit_load_from_flash:
1206 return rval;
1207}
1208
1208static int qla4_8xxx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1209static int qla4_82xx_load_fw(struct scsi_qla_host *ha, uint32_t image_start)
1209{
1210 u32 rst;
1211
1210{
1211 u32 rst;
1212
1212 qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1213 if (qla4_8xxx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
1213 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1214 if (qla4_82xx_pinit_from_rom(ha, 0) != QLA_SUCCESS) {
1214 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1215 __func__);
1216 return QLA_ERROR;
1217 }
1218
1219 udelay(500);
1220
1221 /* at this point, QM is in reset. This could be a problem if there are
1222 * incoming d* transition queue messages. QM/PCIE could wedge.
1223 * To get around this, QM is brought out of reset.
1224 */
1225
1215 printk(KERN_WARNING "%s: Error during CRB Initialization\n",
1216 __func__);
1217 return QLA_ERROR;
1218 }
1219
1220 udelay(500);
1221
1222 /* at this point, QM is in reset. This could be a problem if there are
1223 * incoming d* transition queue messages. QM/PCIE could wedge.
1224 * To get around this, QM is brought out of reset.
1225 */
1226
1226 rst = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
1227 rst = qla4_82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
1227 /* unreset qm */
1228 rst &= ~(1 << 28);
1228 /* unreset qm */
1229 rst &= ~(1 << 28);
1229 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
1230 qla4_82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
1230
1231
1231 if (qla4_8xxx_load_from_flash(ha, image_start)) {
1232 if (qla4_82xx_load_from_flash(ha, image_start)) {
1232 printk("%s: Error trying to load fw from flash!\n", __func__);
1233 return QLA_ERROR;
1234 }
1235
1236 return QLA_SUCCESS;
1237}
1238
1239int
1233 printk("%s: Error trying to load fw from flash!\n", __func__);
1234 return QLA_ERROR;
1235 }
1236
1237 return QLA_SUCCESS;
1238}
1239
1240int
1240qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *ha,
1241qla4_82xx_pci_mem_read_2M(struct scsi_qla_host *ha,
1241 u64 off, void *data, int size)
1242{
1243 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1244 int shift_amount;
1245 uint32_t temp;
1246 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1247
1248 /*
1249 * If not MN, go check for MS or invalid.
1250 */
1251
1252 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1253 mem_crb = QLA82XX_CRB_QDR_NET;
1254 else {
1255 mem_crb = QLA82XX_CRB_DDR_NET;
1242 u64 off, void *data, int size)
1243{
1244 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1245 int shift_amount;
1246 uint32_t temp;
1247 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1248
1249 /*
1250 * If not MN, go check for MS or invalid.
1251 */
1252
1253 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1254 mem_crb = QLA82XX_CRB_QDR_NET;
1255 else {
1256 mem_crb = QLA82XX_CRB_DDR_NET;
1256 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0)
1257 return qla4_8xxx_pci_mem_read_direct(ha,
1257 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1258 return qla4_82xx_pci_mem_read_direct(ha,
1258 off, data, size);
1259 }
1260
1261
1262 off8 = off & 0xfffffff0;
1263 off0[0] = off & 0xf;
1264 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1265 shift_amount = 4;
1266
1267 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1268 off0[1] = 0;
1269 sz[1] = size - sz[0];
1270
1271 for (i = 0; i < loop; i++) {
1272 temp = off8 + (i << shift_amount);
1259 off, data, size);
1260 }
1261
1262
1263 off8 = off & 0xfffffff0;
1264 off0[0] = off & 0xf;
1265 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1266 shift_amount = 4;
1267
1268 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1269 off0[1] = 0;
1270 sz[1] = size - sz[0];
1271
1272 for (i = 0; i < loop; i++) {
1273 temp = off8 + (i << shift_amount);
1273 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1274 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1274 temp = 0;
1275 temp = 0;
1275 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1276 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1276 temp = MIU_TA_CTL_ENABLE;
1277 temp = MIU_TA_CTL_ENABLE;
1277 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1278 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1278 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1279 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1279 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1280 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1280
1281 for (j = 0; j < MAX_CTL_CHECK; j++) {
1281
1282 for (j = 0; j < MAX_CTL_CHECK; j++) {
1282 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1283 temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1283 if ((temp & MIU_TA_CTL_BUSY) == 0)
1284 break;
1285 }
1286
1287 if (j >= MAX_CTL_CHECK) {
1288 printk_ratelimited(KERN_ERR
1289 "%s: failed to read through agent\n",
1290 __func__);
1291 break;
1292 }
1293
1294 start = off0[i] >> 2;
1295 end = (off0[i] + sz[i] - 1) >> 2;
1296 for (k = start; k <= end; k++) {
1284 if ((temp & MIU_TA_CTL_BUSY) == 0)
1285 break;
1286 }
1287
1288 if (j >= MAX_CTL_CHECK) {
1289 printk_ratelimited(KERN_ERR
1290 "%s: failed to read through agent\n",
1291 __func__);
1292 break;
1293 }
1294
1295 start = off0[i] >> 2;
1296 end = (off0[i] + sz[i] - 1) >> 2;
1297 for (k = start; k <= end; k++) {
1297 temp = qla4_8xxx_rd_32(ha,
1298 temp = qla4_82xx_rd_32(ha,
1298 mem_crb + MIU_TEST_AGT_RDDATA(k));
1299 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1300 }
1301 }
1302
1303 if (j >= MAX_CTL_CHECK)
1304 return -1;
1305

--- 17 unchanged lines hidden (view full) ---

1323 case 8:
1324 *(uint64_t *)data = val;
1325 break;
1326 }
1327 return 0;
1328}
1329
1330int
1299 mem_crb + MIU_TEST_AGT_RDDATA(k));
1300 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1301 }
1302 }
1303
1304 if (j >= MAX_CTL_CHECK)
1305 return -1;
1306

--- 17 unchanged lines hidden (view full) ---

1324 case 8:
1325 *(uint64_t *)data = val;
1326 break;
1327 }
1328 return 0;
1329}
1330
1331int
1331qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha,
1332qla4_82xx_pci_mem_write_2M(struct scsi_qla_host *ha,
1332 u64 off, void *data, int size)
1333{
1334 int i, j, ret = 0, loop, sz[2], off0;
1335 int scale, shift_amount, startword;
1336 uint32_t temp;
1337 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1338
1339 /*
1340 * If not MN, go check for MS or invalid.
1341 */
1342 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1343 mem_crb = QLA82XX_CRB_QDR_NET;
1344 else {
1345 mem_crb = QLA82XX_CRB_DDR_NET;
1333 u64 off, void *data, int size)
1334{
1335 int i, j, ret = 0, loop, sz[2], off0;
1336 int scale, shift_amount, startword;
1337 uint32_t temp;
1338 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1339
1340 /*
1341 * If not MN, go check for MS or invalid.
1342 */
1343 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1344 mem_crb = QLA82XX_CRB_QDR_NET;
1345 else {
1346 mem_crb = QLA82XX_CRB_DDR_NET;
1346 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0)
1347 return qla4_8xxx_pci_mem_write_direct(ha,
1347 if (qla4_82xx_pci_mem_bound_check(ha, off, size) == 0)
1348 return qla4_82xx_pci_mem_write_direct(ha,
1348 off, data, size);
1349 }
1350
1351 off0 = off & 0x7;
1352 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1353 sz[1] = size - sz[0];
1354
1355 off8 = off & 0xfffffff0;
1356 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1357 shift_amount = 4;
1358 scale = 2;
1359 startword = (off & 0xf)/8;
1360
1361 for (i = 0; i < loop; i++) {
1349 off, data, size);
1350 }
1351
1352 off0 = off & 0x7;
1353 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1354 sz[1] = size - sz[0];
1355
1356 off8 = off & 0xfffffff0;
1357 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1358 shift_amount = 4;
1359 scale = 2;
1360 startword = (off & 0xf)/8;
1361
1362 for (i = 0; i < loop; i++) {
1362 if (qla4_8xxx_pci_mem_read_2M(ha, off8 +
1363 if (qla4_82xx_pci_mem_read_2M(ha, off8 +
1363 (i << shift_amount), &word[i * scale], 8))
1364 return -1;
1365 }
1366
1367 switch (size) {
1368 case 1:
1369 tmpw = *((uint8_t *)data);
1370 break;

--- 19 unchanged lines hidden (view full) ---

1390
1391 if (sz[1] != 0) {
1392 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1393 word[startword+1] |= tmpw >> (sz[0] * 8);
1394 }
1395
1396 for (i = 0; i < loop; i++) {
1397 temp = off8 + (i << shift_amount);
1364 (i << shift_amount), &word[i * scale], 8))
1365 return -1;
1366 }
1367
1368 switch (size) {
1369 case 1:
1370 tmpw = *((uint8_t *)data);
1371 break;

--- 19 unchanged lines hidden (view full) ---

1391
1392 if (sz[1] != 0) {
1393 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1394 word[startword+1] |= tmpw >> (sz[0] * 8);
1395 }
1396
1397 for (i = 0; i < loop; i++) {
1398 temp = off8 + (i << shift_amount);
1398 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1399 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1399 temp = 0;
1400 temp = 0;
1400 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1401 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1401 temp = word[i * scale] & 0xffffffff;
1402 temp = word[i * scale] & 0xffffffff;
1402 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1403 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1403 temp = (word[i * scale] >> 32) & 0xffffffff;
1404 temp = (word[i * scale] >> 32) & 0xffffffff;
1404 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1405 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1405 temp = word[i*scale + 1] & 0xffffffff;
1406 temp = word[i*scale + 1] & 0xffffffff;
1406 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1407 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO,
1407 temp);
1408 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1408 temp);
1409 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1409 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1410 qla4_82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI,
1410 temp);
1411
1412 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1411 temp);
1412
1413 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1413 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1414 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1414 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1415 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1415 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1416 qla4_82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp);
1416
1417 for (j = 0; j < MAX_CTL_CHECK; j++) {
1417
1418 for (j = 0; j < MAX_CTL_CHECK; j++) {
1418 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1419 temp = qla4_82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1419 if ((temp & MIU_TA_CTL_BUSY) == 0)
1420 break;
1421 }
1422
1423 if (j >= MAX_CTL_CHECK) {
1424 if (printk_ratelimit())
1425 ql4_printk(KERN_ERR, ha,
1426 "%s: failed to read through agent\n",
1427 __func__);
1428 ret = -1;
1429 break;
1430 }
1431 }
1432
1433 return ret;
1434}
1435
1420 if ((temp & MIU_TA_CTL_BUSY) == 0)
1421 break;
1422 }
1423
1424 if (j >= MAX_CTL_CHECK) {
1425 if (printk_ratelimit())
1426 ql4_printk(KERN_ERR, ha,
1427 "%s: failed to read through agent\n",
1428 __func__);
1429 ret = -1;
1430 break;
1431 }
1432 }
1433
1434 return ret;
1435}
1436
1436static int qla4_8xxx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1437static int qla4_82xx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val)
1437{
1438 u32 val = 0;
1439 int retries = 60;
1440
1441 if (!pegtune_val) {
1442 do {
1438{
1439 u32 val = 0;
1440 int retries = 60;
1441
1442 if (!pegtune_val) {
1443 do {
1443 val = qla4_8xxx_rd_32(ha, CRB_CMDPEG_STATE);
1444 val = qla4_82xx_rd_32(ha, CRB_CMDPEG_STATE);
1444 if ((val == PHAN_INITIALIZE_COMPLETE) ||
1445 (val == PHAN_INITIALIZE_ACK))
1446 return 0;
1447 set_current_state(TASK_UNINTERRUPTIBLE);
1448 schedule_timeout(500);
1449
1450 } while (--retries);
1451
1452 if (!retries) {
1445 if ((val == PHAN_INITIALIZE_COMPLETE) ||
1446 (val == PHAN_INITIALIZE_ACK))
1447 return 0;
1448 set_current_state(TASK_UNINTERRUPTIBLE);
1449 schedule_timeout(500);
1450
1451 } while (--retries);
1452
1453 if (!retries) {
1453 pegtune_val = qla4_8xxx_rd_32(ha,
1454 pegtune_val = qla4_82xx_rd_32(ha,
1454 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1455 printk(KERN_WARNING "%s: init failed, "
1456 "pegtune_val = %x\n", __func__, pegtune_val);
1457 return -1;
1458 }
1459 }
1460 return 0;
1461}
1462
1455 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1456 printk(KERN_WARNING "%s: init failed, "
1457 "pegtune_val = %x\n", __func__, pegtune_val);
1458 return -1;
1459 }
1460 }
1461 return 0;
1462}
1463
1463static int qla4_8xxx_rcvpeg_ready(struct scsi_qla_host *ha)
1464static int qla4_82xx_rcvpeg_ready(struct scsi_qla_host *ha)
1464{
1465 uint32_t state = 0;
1466 int loops = 0;
1467
1468 /* Window 1 call */
1469 read_lock(&ha->hw_lock);
1465{
1466 uint32_t state = 0;
1467 int loops = 0;
1468
1469 /* Window 1 call */
1470 read_lock(&ha->hw_lock);
1470 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE);
1471 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1471 read_unlock(&ha->hw_lock);
1472
1473 while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1474 udelay(100);
1475 /* Window 1 call */
1476 read_lock(&ha->hw_lock);
1472 read_unlock(&ha->hw_lock);
1473
1474 while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) {
1475 udelay(100);
1476 /* Window 1 call */
1477 read_lock(&ha->hw_lock);
1477 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE);
1478 state = qla4_82xx_rd_32(ha, CRB_RCVPEG_STATE);
1478 read_unlock(&ha->hw_lock);
1479
1480 loops++;
1481 }
1482
1483 if (loops >= 30000) {
1484 DEBUG2(ql4_printk(KERN_INFO, ha,
1485 "Receive Peg initialization not complete: 0x%x.\n", state));
1486 return QLA_ERROR;
1487 }
1488
1489 return QLA_SUCCESS;
1490}
1491
1492void
1493qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1494{
1495 uint32_t drv_active;
1496
1479 read_unlock(&ha->hw_lock);
1480
1481 loops++;
1482 }
1483
1484 if (loops >= 30000) {
1485 DEBUG2(ql4_printk(KERN_INFO, ha,
1486 "Receive Peg initialization not complete: 0x%x.\n", state));
1487 return QLA_ERROR;
1488 }
1489
1490 return QLA_SUCCESS;
1491}
1492
1493void
1494qla4_8xxx_set_drv_active(struct scsi_qla_host *ha)
1495{
1496 uint32_t drv_active;
1497
1497 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1498 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1498 drv_active |= (1 << (ha->func_num * 4));
1499 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1500 __func__, ha->host_no, drv_active);
1499 drv_active |= (1 << (ha->func_num * 4));
1500 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1501 __func__, ha->host_no, drv_active);
1501 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1502 qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1502}
1503
1504void
1505qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1506{
1507 uint32_t drv_active;
1508
1503}
1504
1505void
1506qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha)
1507{
1508 uint32_t drv_active;
1509
1509 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1510 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1510 drv_active &= ~(1 << (ha->func_num * 4));
1511 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1512 __func__, ha->host_no, drv_active);
1511 drv_active &= ~(1 << (ha->func_num * 4));
1512 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_active: 0x%08x\n",
1513 __func__, ha->host_no, drv_active);
1513 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1514 qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
1514}
1515
1516static inline int
1517qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1518{
1519 uint32_t drv_state, drv_active;
1520 int rval;
1521
1515}
1516
1517static inline int
1518qla4_8xxx_need_reset(struct scsi_qla_host *ha)
1519{
1520 uint32_t drv_state, drv_active;
1521 int rval;
1522
1522 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1523 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1523 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
1524 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1524 rval = drv_state & (1 << (ha->func_num * 4));
1525 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1526 rval = 1;
1527
1528 return rval;
1529}
1530
1531static inline void
1532qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1533{
1534 uint32_t drv_state;
1535
1525 rval = drv_state & (1 << (ha->func_num * 4));
1526 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active)
1527 rval = 1;
1528
1529 return rval;
1530}
1531
1532static inline void
1533qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha)
1534{
1535 uint32_t drv_state;
1536
1536 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1537 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1537 drv_state |= (1 << (ha->func_num * 4));
1538 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1539 __func__, ha->host_no, drv_state);
1538 drv_state |= (1 << (ha->func_num * 4));
1539 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1540 __func__, ha->host_no, drv_state);
1540 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1541 qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1541}
1542
1543static inline void
1544qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1545{
1546 uint32_t drv_state;
1547
1542}
1543
1544static inline void
1545qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha)
1546{
1547 uint32_t drv_state;
1548
1548 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1549 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1549 drv_state &= ~(1 << (ha->func_num * 4));
1550 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1551 __func__, ha->host_no, drv_state);
1550 drv_state &= ~(1 << (ha->func_num * 4));
1551 ql4_printk(KERN_INFO, ha, "%s(%ld): drv_state: 0x%08x\n",
1552 __func__, ha->host_no, drv_state);
1552 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1553 qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
1553}
1554
1555static inline void
1556qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1557{
1558 uint32_t qsnt_state;
1559
1554}
1555
1556static inline void
1557qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha)
1558{
1559 uint32_t qsnt_state;
1560
1560 qsnt_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1561 qsnt_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
1561 qsnt_state |= (2 << (ha->func_num * 4));
1562 qsnt_state |= (2 << (ha->func_num * 4));
1562 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
1563 qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
1563}
1564
1565
1566static int
1564}
1565
1566
1567static int
1567qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1568qla4_82xx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start)
1568{
1569 int pcie_cap;
1570 uint16_t lnk;
1571
1572 /* scrub dma mask expansion register */
1569{
1570 int pcie_cap;
1571 uint16_t lnk;
1572
1573 /* scrub dma mask expansion register */
1573 qla4_8xxx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
1574 qla4_82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555);
1574
1575 /* Overwrite stale initialization register values */
1575
1576 /* Overwrite stale initialization register values */
1576 qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1577 qla4_8xxx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1578 qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1579 qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
1577 qla4_82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
1578 qla4_82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
1579 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
1580 qla4_82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
1580
1581
1581 if (qla4_8xxx_load_fw(ha, image_start) != QLA_SUCCESS) {
1582 if (qla4_82xx_load_fw(ha, image_start) != QLA_SUCCESS) {
1582 printk("%s: Error trying to start fw!\n", __func__);
1583 return QLA_ERROR;
1584 }
1585
1586 /* Handshake with the card before we register the devices. */
1583 printk("%s: Error trying to start fw!\n", __func__);
1584 return QLA_ERROR;
1585 }
1586
1587 /* Handshake with the card before we register the devices. */
1587 if (qla4_8xxx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
1588 if (qla4_82xx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) {
1588 printk("%s: Error during card handshake!\n", __func__);
1589 return QLA_ERROR;
1590 }
1591
1592 /* Negotiated Link width */
1593 pcie_cap = pci_pcie_cap(ha->pdev);
1594 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
1595 ha->link_width = (lnk >> 4) & 0x3f;
1596
1597 /* Synchronize with Receive peg */
1589 printk("%s: Error during card handshake!\n", __func__);
1590 return QLA_ERROR;
1591 }
1592
1593 /* Negotiated Link width */
1594 pcie_cap = pci_pcie_cap(ha->pdev);
1595 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk);
1596 ha->link_width = (lnk >> 4) & 0x3f;
1597
1598 /* Synchronize with Receive peg */
1598 return qla4_8xxx_rcvpeg_ready(ha);
1599 return qla4_82xx_rcvpeg_ready(ha);
1599}
1600
1601static int
1600}
1601
1602static int
1602qla4_8xxx_try_start_fw(struct scsi_qla_host *ha)
1603qla4_82xx_try_start_fw(struct scsi_qla_host *ha)
1603{
1604 int rval = QLA_ERROR;
1605
1606 /*
1607 * FW Load priority:
1608 * 1) Operational firmware residing in flash.
1609 * 2) Fail
1610 */
1611
1612 ql4_printk(KERN_INFO, ha,
1613 "FW: Retrieving flash offsets from FLT/FDT ...\n");
1614 rval = qla4_8xxx_get_flash_info(ha);
1615 if (rval != QLA_SUCCESS)
1616 return rval;
1617
1618 ql4_printk(KERN_INFO, ha,
1619 "FW: Attempting to load firmware from flash...\n");
1604{
1605 int rval = QLA_ERROR;
1606
1607 /*
1608 * FW Load priority:
1609 * 1) Operational firmware residing in flash.
1610 * 2) Fail
1611 */
1612
1613 ql4_printk(KERN_INFO, ha,
1614 "FW: Retrieving flash offsets from FLT/FDT ...\n");
1615 rval = qla4_8xxx_get_flash_info(ha);
1616 if (rval != QLA_SUCCESS)
1617 return rval;
1618
1619 ql4_printk(KERN_INFO, ha,
1620 "FW: Attempting to load firmware from flash...\n");
1620 rval = qla4_8xxx_start_firmware(ha, ha->hw.flt_region_fw);
1621 rval = qla4_82xx_start_firmware(ha, ha->hw.flt_region_fw);
1621
1622 if (rval != QLA_SUCCESS) {
1623 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1624 " FAILED...\n");
1625 return rval;
1626 }
1627
1628 return rval;
1629}
1630
1622
1623 if (rval != QLA_SUCCESS) {
1624 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash"
1625 " FAILED...\n");
1626 return rval;
1627 }
1628
1629 return rval;
1630}
1631
1631static void qla4_8xxx_rom_lock_recovery(struct scsi_qla_host *ha)
1632static void qla4_82xx_rom_lock_recovery(struct scsi_qla_host *ha)
1632{
1633{
1633 if (qla4_8xxx_rom_lock(ha)) {
1634 if (qla4_82xx_rom_lock(ha)) {
1634 /* Someone else is holding the lock. */
1635 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1636 }
1637
1638 /*
1639 * Either we got the lock, or someone
1640 * else died while holding it.
1641 * In either case, unlock.
1642 */
1635 /* Someone else is holding the lock. */
1636 dev_info(&ha->pdev->dev, "Resetting rom_lock\n");
1637 }
1638
1639 /*
1640 * Either we got the lock, or someone
1641 * else died while holding it.
1642 * In either case, unlock.
1643 */
1643 qla4_8xxx_rom_unlock(ha);
1644 qla4_82xx_rom_unlock(ha);
1644}
1645
1646static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
1647 struct qla82xx_minidump_entry_hdr *entry_hdr,
1648 uint32_t **d_ptr)
1649{
1650 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
1651 struct qla82xx_minidump_entry_crb *crb_hdr;

--- 208 unchanged lines hidden (view full) ---

1860 __func__, r_addr, r_stride, loop_cnt));
1861
1862 for (i = 0; i < loop_cnt; i++) {
1863 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
1864 *data_ptr++ = cpu_to_le32(r_value);
1865 r_addr += r_stride;
1866 }
1867 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
1645}
1646
1647static void qla4_8xxx_minidump_process_rdcrb(struct scsi_qla_host *ha,
1648 struct qla82xx_minidump_entry_hdr *entry_hdr,
1649 uint32_t **d_ptr)
1650{
1651 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
1652 struct qla82xx_minidump_entry_crb *crb_hdr;

--- 208 unchanged lines hidden (view full) ---

1861 __func__, r_addr, r_stride, loop_cnt));
1862
1863 for (i = 0; i < loop_cnt; i++) {
1864 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
1865 *data_ptr++ = cpu_to_le32(r_value);
1866 r_addr += r_stride;
1867 }
1868 DEBUG2(ql4_printk(KERN_INFO, ha, "Leaving fn: %s datacount: 0x%lx\n",
1868 __func__, (loop_cnt * sizeof(uint32_t))));
1869 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))));
1869 *d_ptr = data_ptr;
1870}
1871
1872static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
1873 struct qla82xx_minidump_entry_hdr *entry_hdr,
1874 uint32_t **d_ptr)
1875{
1876 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;

--- 80 unchanged lines hidden (view full) ---

1957 qid += q_hdr->q_strd.queue_id_stride;
1958 }
1959 *d_ptr = data_ptr;
1960}
1961
1962#define MD_DIRECT_ROM_WINDOW 0x42110030
1963#define MD_DIRECT_ROM_READ_BASE 0x42150000
1964
1870 *d_ptr = data_ptr;
1871}
1872
1873static void qla4_8xxx_minidump_process_rdmux(struct scsi_qla_host *ha,
1874 struct qla82xx_minidump_entry_hdr *entry_hdr,
1875 uint32_t **d_ptr)
1876{
1877 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;

--- 80 unchanged lines hidden (view full) ---

1958 qid += q_hdr->q_strd.queue_id_stride;
1959 }
1960 *d_ptr = data_ptr;
1961}
1962
1963#define MD_DIRECT_ROM_WINDOW 0x42110030
1964#define MD_DIRECT_ROM_READ_BASE 0x42150000
1965
1965static void qla4_8xxx_minidump_process_rdrom(struct scsi_qla_host *ha,
1966static void qla4_82xx_minidump_process_rdrom(struct scsi_qla_host *ha,
1966 struct qla82xx_minidump_entry_hdr *entry_hdr,
1967 uint32_t **d_ptr)
1968{
1969 uint32_t r_addr, r_value;
1970 uint32_t i, loop_cnt;
1971 struct qla82xx_minidump_entry_rdrom *rom_hdr;
1972 uint32_t *data_ptr = *d_ptr;
1973

--- 109 unchanged lines hidden (view full) ---

2083 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
2084 DEBUG2(ql4_printk(KERN_INFO, ha,
2085 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2086 ha->host_no, index, entry_hdr->entry_type,
2087 entry_hdr->d_ctrl.entry_capture_mask));
2088}
2089
2090/**
1967 struct qla82xx_minidump_entry_hdr *entry_hdr,
1968 uint32_t **d_ptr)
1969{
1970 uint32_t r_addr, r_value;
1971 uint32_t i, loop_cnt;
1972 struct qla82xx_minidump_entry_rdrom *rom_hdr;
1973 uint32_t *data_ptr = *d_ptr;
1974

--- 109 unchanged lines hidden (view full) ---

2084 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
2085 DEBUG2(ql4_printk(KERN_INFO, ha,
2086 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
2087 ha->host_no, index, entry_hdr->entry_type,
2088 entry_hdr->d_ctrl.entry_capture_mask));
2089}
2090
2091/**
2091 * qla82xx_collect_md_data - Retrieve firmware minidump data.
2092 * qla4_8xxx_collect_md_data - Retrieve firmware minidump data.
2092 * @ha: pointer to adapter structure
2093 **/
2094static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2095{
2096 int num_entry_hdr = 0;
2097 struct qla82xx_minidump_entry_hdr *entry_hdr;
2098 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2099 uint32_t *data_ptr;

--- 79 unchanged lines hidden (view full) ---

2179 &data_ptr);
2180 if (rval != QLA_SUCCESS) {
2181 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2182 goto md_failed;
2183 }
2184 break;
2185 case QLA82XX_BOARD:
2186 case QLA82XX_RDROM:
2093 * @ha: pointer to adapter structure
2094 **/
2095static int qla4_8xxx_collect_md_data(struct scsi_qla_host *ha)
2096{
2097 int num_entry_hdr = 0;
2098 struct qla82xx_minidump_entry_hdr *entry_hdr;
2099 struct qla4_8xxx_minidump_template_hdr *tmplt_hdr;
2100 uint32_t *data_ptr;

--- 79 unchanged lines hidden (view full) ---

2180 &data_ptr);
2181 if (rval != QLA_SUCCESS) {
2182 ql4_8xxx_mark_entry_skipped(ha, entry_hdr, i);
2183 goto md_failed;
2184 }
2185 break;
2186 case QLA82XX_BOARD:
2187 case QLA82XX_RDROM:
2187 qla4_8xxx_minidump_process_rdrom(ha, entry_hdr,
2188 qla4_82xx_minidump_process_rdrom(ha, entry_hdr,
2188 &data_ptr);
2189 break;
2190 case QLA82XX_L2DTG:
2191 case QLA82XX_L2ITG:
2192 case QLA82XX_L2DAT:
2193 case QLA82XX_L2INS:
2194 rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
2195 &data_ptr);

--- 81 unchanged lines hidden (view full) ---

2277{
2278 int rval = QLA_ERROR;
2279 int i, timeout;
2280 uint32_t old_count, count;
2281 int need_reset = 0, peg_stuck = 1;
2282
2283 need_reset = qla4_8xxx_need_reset(ha);
2284
2189 &data_ptr);
2190 break;
2191 case QLA82XX_L2DTG:
2192 case QLA82XX_L2ITG:
2193 case QLA82XX_L2DAT:
2194 case QLA82XX_L2INS:
2195 rval = qla4_8xxx_minidump_process_l2tag(ha, entry_hdr,
2196 &data_ptr);

--- 81 unchanged lines hidden (view full) ---

2278{
2279 int rval = QLA_ERROR;
2280 int i, timeout;
2281 uint32_t old_count, count;
2282 int need_reset = 0, peg_stuck = 1;
2283
2284 need_reset = qla4_8xxx_need_reset(ha);
2285
2285 old_count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2286 old_count = qla4_82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2286
2287 for (i = 0; i < 10; i++) {
2288 timeout = msleep_interruptible(200);
2289 if (timeout) {
2287
2288 for (i = 0; i < 10; i++) {
2289 timeout = msleep_interruptible(200);
2290 if (timeout) {
2290 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2291 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2291 QLA82XX_DEV_FAILED);
2292 return rval;
2293 }
2294
2292 QLA82XX_DEV_FAILED);
2293 return rval;
2294 }
2295
2295 count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2296 count = qla4_82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2296 if (count != old_count)
2297 peg_stuck = 0;
2298 }
2299
2300 if (need_reset) {
2301 /* We are trying to perform a recovery here. */
2302 if (peg_stuck)
2297 if (count != old_count)
2298 peg_stuck = 0;
2299 }
2300
2301 if (need_reset) {
2302 /* We are trying to perform a recovery here. */
2303 if (peg_stuck)
2303 qla4_8xxx_rom_lock_recovery(ha);
2304 qla4_82xx_rom_lock_recovery(ha);
2304 goto dev_initialize;
2305 } else {
2306 /* Start of day for this ha context. */
2307 if (peg_stuck) {
2308 /* Either we are the first or recovery in progress. */
2305 goto dev_initialize;
2306 } else {
2307 /* Start of day for this ha context. */
2308 if (peg_stuck) {
2309 /* Either we are the first or recovery in progress. */
2309 qla4_8xxx_rom_lock_recovery(ha);
2310 qla4_82xx_rom_lock_recovery(ha);
2310 goto dev_initialize;
2311 } else {
2312 /* Firmware already running. */
2313 rval = QLA_SUCCESS;
2314 goto dev_ready;
2315 }
2316 }
2317
2318dev_initialize:
2319 /* set to DEV_INITIALIZING */
2320 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
2311 goto dev_initialize;
2312 } else {
2313 /* Firmware already running. */
2314 rval = QLA_SUCCESS;
2315 goto dev_ready;
2316 }
2317 }
2318
2319dev_initialize:
2320 /* set to DEV_INITIALIZING */
2321 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n");
2321 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING);
2322 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING);
2322
2323 /* Driver that sets device state to initializating sets IDC version */
2323
2324 /* Driver that sets device state to initializating sets IDC version */
2324 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION);
2325 qla4_82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION);
2325
2326
2326 qla4_8xxx_idc_unlock(ha);
2327 qla4_82xx_idc_unlock(ha);
2327 if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
2328 !test_and_set_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
2329 if (!qla4_8xxx_collect_md_data(ha)) {
2330 qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
2331 } else {
2332 ql4_printk(KERN_INFO, ha, "Unable to collect minidump\n");
2333 clear_bit(AF_82XX_FW_DUMPED, &ha->flags);
2334 }
2335 }
2328 if (ql4xenablemd && test_bit(AF_FW_RECOVERY, &ha->flags) &&
2329 !test_and_set_bit(AF_82XX_FW_DUMPED, &ha->flags)) {
2330 if (!qla4_8xxx_collect_md_data(ha)) {
2331 qla4_8xxx_uevent_emit(ha, QL4_UEVENT_CODE_FW_DUMP);
2332 } else {
2333 ql4_printk(KERN_INFO, ha, "Unable to collect minidump\n");
2334 clear_bit(AF_82XX_FW_DUMPED, &ha->flags);
2335 }
2336 }
2336 rval = qla4_8xxx_try_start_fw(ha);
2337 qla4_8xxx_idc_lock(ha);
2337 rval = qla4_82xx_try_start_fw(ha);
2338 qla4_82xx_idc_lock(ha);
2338
2339 if (rval != QLA_SUCCESS) {
2340 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
2341 qla4_8xxx_clear_drv_active(ha);
2339
2340 if (rval != QLA_SUCCESS) {
2341 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n");
2342 qla4_8xxx_clear_drv_active(ha);
2342 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED);
2343 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED);
2343 return rval;
2344 }
2345
2346dev_ready:
2347 ql4_printk(KERN_INFO, ha, "HW State: READY\n");
2344 return rval;
2345 }
2346
2347dev_ready:
2348 ql4_printk(KERN_INFO, ha, "HW State: READY\n");
2348 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY);
2349 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY);
2349
2350 return rval;
2351}
2352
2353/**
2350
2351 return rval;
2352}
2353
2354/**
2354 * qla4_8xxx_need_reset_handler - Code to start reset sequence
2355 * qla4_82xx_need_reset_handler - Code to start reset sequence
2355 * @ha: pointer to adapter structure
2356 *
2357 * Note: IDC lock must be held upon entry
2358 **/
2359static void
2356 * @ha: pointer to adapter structure
2357 *
2358 * Note: IDC lock must be held upon entry
2359 **/
2360static void
2360qla4_8xxx_need_reset_handler(struct scsi_qla_host *ha)
2361qla4_82xx_need_reset_handler(struct scsi_qla_host *ha)
2361{
2362 uint32_t dev_state, drv_state, drv_active;
2363 uint32_t active_mask = 0xFFFFFFFF;
2364 unsigned long reset_timeout;
2365
2366 ql4_printk(KERN_INFO, ha,
2367 "Performing ISP error recovery\n");
2368
2369 if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
2362{
2363 uint32_t dev_state, drv_state, drv_active;
2364 uint32_t active_mask = 0xFFFFFFFF;
2365 unsigned long reset_timeout;
2366
2367 ql4_printk(KERN_INFO, ha,
2368 "Performing ISP error recovery\n");
2369
2370 if (test_and_clear_bit(AF_ONLINE, &ha->flags)) {
2370 qla4_8xxx_idc_unlock(ha);
2371 qla4_82xx_idc_unlock(ha);
2371 ha->isp_ops->disable_intrs(ha);
2372 ha->isp_ops->disable_intrs(ha);
2372 qla4_8xxx_idc_lock(ha);
2373 qla4_82xx_idc_lock(ha);
2373 }
2374
2375 if (!test_bit(AF_82XX_RST_OWNER, &ha->flags)) {
2376 DEBUG2(ql4_printk(KERN_INFO, ha,
2377 "%s(%ld): reset acknowledged\n",
2378 __func__, ha->host_no));
2379 qla4_8xxx_set_rst_ready(ha);
2380 } else {
2381 active_mask = (~(1 << (ha->func_num * 4)));
2382 }
2383
2384 /* wait for 10 seconds for reset ack from all functions */
2385 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
2386
2374 }
2375
2376 if (!test_bit(AF_82XX_RST_OWNER, &ha->flags)) {
2377 DEBUG2(ql4_printk(KERN_INFO, ha,
2378 "%s(%ld): reset acknowledged\n",
2379 __func__, ha->host_no));
2380 qla4_8xxx_set_rst_ready(ha);
2381 } else {
2382 active_mask = (~(1 << (ha->func_num * 4)));
2383 }
2384
2385 /* wait for 10 seconds for reset ack from all functions */
2386 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ);
2387
2387 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2388 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2388 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2389 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2389
2390 ql4_printk(KERN_INFO, ha,
2391 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2392 __func__, ha->host_no, drv_state, drv_active);
2393
2394 while (drv_state != (drv_active & active_mask)) {
2395 if (time_after_eq(jiffies, reset_timeout)) {
2396 ql4_printk(KERN_INFO, ha,

--- 7 unchanged lines hidden (view full) ---

2404 * acked/did not ack
2405 */
2406 if (test_bit(AF_82XX_RST_OWNER, &ha->flags)) {
2407 ql4_printk(KERN_INFO, ha,
2408 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2409 __func__, ha->host_no, drv_state,
2410 drv_active);
2411 }
2390
2391 ql4_printk(KERN_INFO, ha,
2392 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2393 __func__, ha->host_no, drv_state, drv_active);
2394
2395 while (drv_state != (drv_active & active_mask)) {
2396 if (time_after_eq(jiffies, reset_timeout)) {
2397 ql4_printk(KERN_INFO, ha,

--- 7 unchanged lines hidden (view full) ---

2405 * acked/did not ack
2406 */
2407 if (test_bit(AF_82XX_RST_OWNER, &ha->flags)) {
2408 ql4_printk(KERN_INFO, ha,
2409 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n",
2410 __func__, ha->host_no, drv_state,
2411 drv_active);
2412 }
2412 qla4_8xxx_idc_unlock(ha);
2413 qla4_82xx_idc_unlock(ha);
2413 msleep(1000);
2414 msleep(1000);
2414 qla4_8xxx_idc_lock(ha);
2415 qla4_82xx_idc_lock(ha);
2415
2416
2416 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2417 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2417 drv_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2418 drv_active = qla4_82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2418 }
2419
2420 /* Clear RESET OWNER as we are not going to use it any further */
2421 clear_bit(AF_82XX_RST_OWNER, &ha->flags);
2422
2419 }
2420
2421 /* Clear RESET OWNER as we are not going to use it any further */
2422 clear_bit(AF_82XX_RST_OWNER, &ha->flags);
2423
2423 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2424 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2424 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
2425 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
2426
2427 /* Force to DEV_COLD unless someone else is starting a reset */
2428 if (dev_state != QLA82XX_DEV_INITIALIZING) {
2429 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
2425 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n", dev_state,
2426 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown");
2427
2428 /* Force to DEV_COLD unless someone else is starting a reset */
2429 if (dev_state != QLA82XX_DEV_INITIALIZING) {
2430 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n");
2430 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD);
2431 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD);
2431 qla4_8xxx_set_rst_ready(ha);
2432 }
2433}
2434
2435/**
2436 * qla4_8xxx_need_qsnt_handler - Code to start qsnt
2437 * @ha: pointer to adapter structure
2438 **/
2439void
2440qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
2441{
2432 qla4_8xxx_set_rst_ready(ha);
2433 }
2434}
2435
2436/**
2437 * qla4_8xxx_need_qsnt_handler - Code to start qsnt
2438 * @ha: pointer to adapter structure
2439 **/
2440void
2441qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha)
2442{
2442 qla4_8xxx_idc_lock(ha);
2443 qla4_82xx_idc_lock(ha);
2443 qla4_8xxx_set_qsnt_ready(ha);
2444 qla4_8xxx_set_qsnt_ready(ha);
2444 qla4_8xxx_idc_unlock(ha);
2445 qla4_82xx_idc_unlock(ha);
2445}
2446
2447/**
2448 * qla4_8xxx_device_state_handler - Adapter state machine
2449 * @ha: pointer to host adapter structure.
2450 *
2451 * Note: IDC lock must be UNLOCKED upon entry
2452 **/
2453int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
2454{
2455 uint32_t dev_state;
2456 int rval = QLA_SUCCESS;
2457 unsigned long dev_init_timeout;
2458
2459 if (!test_bit(AF_INIT_DONE, &ha->flags)) {
2446}
2447
2448/**
2449 * qla4_8xxx_device_state_handler - Adapter state machine
2450 * @ha: pointer to host adapter structure.
2451 *
2452 * Note: IDC lock must be UNLOCKED upon entry
2453 **/
2454int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha)
2455{
2456 uint32_t dev_state;
2457 int rval = QLA_SUCCESS;
2458 unsigned long dev_init_timeout;
2459
2460 if (!test_bit(AF_INIT_DONE, &ha->flags)) {
2460 qla4_8xxx_idc_lock(ha);
2461 qla4_82xx_idc_lock(ha);
2461 qla4_8xxx_set_drv_active(ha);
2462 qla4_8xxx_set_drv_active(ha);
2462 qla4_8xxx_idc_unlock(ha);
2463 qla4_82xx_idc_unlock(ha);
2463 }
2464
2464 }
2465
2465 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2466 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2466 DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
2467 dev_state, dev_state < MAX_STATES ?
2468 qdev_state[dev_state] : "Unknown"));
2469
2470 /* wait for 30 seconds for device to go ready */
2471 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
2472
2467 DEBUG2(ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
2468 dev_state, dev_state < MAX_STATES ?
2469 qdev_state[dev_state] : "Unknown"));
2470
2471 /* wait for 30 seconds for device to go ready */
2472 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ);
2473
2473 qla4_8xxx_idc_lock(ha);
2474 qla4_82xx_idc_lock(ha);
2474 while (1) {
2475
2476 if (time_after_eq(jiffies, dev_init_timeout)) {
2477 ql4_printk(KERN_WARNING, ha,
2478 "%s: Device Init Failed 0x%x = %s\n",
2479 DRIVER_NAME,
2480 dev_state, dev_state < MAX_STATES ?
2481 qdev_state[dev_state] : "Unknown");
2475 while (1) {
2476
2477 if (time_after_eq(jiffies, dev_init_timeout)) {
2478 ql4_printk(KERN_WARNING, ha,
2479 "%s: Device Init Failed 0x%x = %s\n",
2480 DRIVER_NAME,
2481 dev_state, dev_state < MAX_STATES ?
2482 qdev_state[dev_state] : "Unknown");
2482 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2483 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2483 QLA82XX_DEV_FAILED);
2484 }
2485
2484 QLA82XX_DEV_FAILED);
2485 }
2486
2486 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2487 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2487 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
2488 dev_state, dev_state < MAX_STATES ?
2489 qdev_state[dev_state] : "Unknown");
2490
2491 /* NOTE: Make sure idc unlocked upon exit of switch statement */
2492 switch (dev_state) {
2493 case QLA82XX_DEV_READY:
2494 goto exit;
2495 case QLA82XX_DEV_COLD:
2496 rval = qla4_8xxx_device_bootstrap(ha);
2497 goto exit;
2498 case QLA82XX_DEV_INITIALIZING:
2488 ql4_printk(KERN_INFO, ha, "Device state is 0x%x = %s\n",
2489 dev_state, dev_state < MAX_STATES ?
2490 qdev_state[dev_state] : "Unknown");
2491
2492 /* NOTE: Make sure idc unlocked upon exit of switch statement */
2493 switch (dev_state) {
2494 case QLA82XX_DEV_READY:
2495 goto exit;
2496 case QLA82XX_DEV_COLD:
2497 rval = qla4_8xxx_device_bootstrap(ha);
2498 goto exit;
2499 case QLA82XX_DEV_INITIALIZING:
2499 qla4_8xxx_idc_unlock(ha);
2500 qla4_82xx_idc_unlock(ha);
2500 msleep(1000);
2501 msleep(1000);
2501 qla4_8xxx_idc_lock(ha);
2502 qla4_82xx_idc_lock(ha);
2502 break;
2503 case QLA82XX_DEV_NEED_RESET:
2504 if (!ql4xdontresethba) {
2503 break;
2504 case QLA82XX_DEV_NEED_RESET:
2505 if (!ql4xdontresethba) {
2505 qla4_8xxx_need_reset_handler(ha);
2506 qla4_82xx_need_reset_handler(ha);
2506 /* Update timeout value after need
2507 * reset handler */
2508 dev_init_timeout = jiffies +
2509 (ha->nx_dev_init_timeout * HZ);
2510 } else {
2507 /* Update timeout value after need
2508 * reset handler */
2509 dev_init_timeout = jiffies +
2510 (ha->nx_dev_init_timeout * HZ);
2511 } else {
2511 qla4_8xxx_idc_unlock(ha);
2512 qla4_82xx_idc_unlock(ha);
2512 msleep(1000);
2513 msleep(1000);
2513 qla4_8xxx_idc_lock(ha);
2514 qla4_82xx_idc_lock(ha);
2514 }
2515 break;
2516 case QLA82XX_DEV_NEED_QUIESCENT:
2517 /* idc locked/unlocked in handler */
2518 qla4_8xxx_need_qsnt_handler(ha);
2519 break;
2520 case QLA82XX_DEV_QUIESCENT:
2515 }
2516 break;
2517 case QLA82XX_DEV_NEED_QUIESCENT:
2518 /* idc locked/unlocked in handler */
2519 qla4_8xxx_need_qsnt_handler(ha);
2520 break;
2521 case QLA82XX_DEV_QUIESCENT:
2521 qla4_8xxx_idc_unlock(ha);
2522 qla4_82xx_idc_unlock(ha);
2522 msleep(1000);
2523 msleep(1000);
2523 qla4_8xxx_idc_lock(ha);
2524 qla4_82xx_idc_lock(ha);
2524 break;
2525 case QLA82XX_DEV_FAILED:
2525 break;
2526 case QLA82XX_DEV_FAILED:
2526 qla4_8xxx_idc_unlock(ha);
2527 qla4_82xx_idc_unlock(ha);
2527 qla4xxx_dead_adapter_cleanup(ha);
2528 rval = QLA_ERROR;
2528 qla4xxx_dead_adapter_cleanup(ha);
2529 rval = QLA_ERROR;
2529 qla4_8xxx_idc_lock(ha);
2530 qla4_82xx_idc_lock(ha);
2530 goto exit;
2531 default:
2531 goto exit;
2532 default:
2532 qla4_8xxx_idc_unlock(ha);
2533 qla4_82xx_idc_unlock(ha);
2533 qla4xxx_dead_adapter_cleanup(ha);
2534 rval = QLA_ERROR;
2534 qla4xxx_dead_adapter_cleanup(ha);
2535 rval = QLA_ERROR;
2535 qla4_8xxx_idc_lock(ha);
2536 qla4_82xx_idc_lock(ha);
2536 goto exit;
2537 }
2538 }
2539exit:
2537 goto exit;
2538 }
2539 }
2540exit:
2540 qla4_8xxx_idc_unlock(ha);
2541 qla4_82xx_idc_unlock(ha);
2541 return rval;
2542}
2543
2544int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
2545{
2546 int retval;
2547
2548 /* clear the interrupt */

--- 27 unchanged lines hidden (view full) ---

2576
2577static inline uint32_t
2578flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
2579{
2580 return hw->flash_data_off | faddr;
2581}
2582
2583static uint32_t *
2542 return rval;
2543}
2544
2545int qla4_8xxx_load_risc(struct scsi_qla_host *ha)
2546{
2547 int retval;
2548
2549 /* clear the interrupt */

--- 27 unchanged lines hidden (view full) ---

2577
2578static inline uint32_t
2579flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr)
2580{
2581 return hw->flash_data_off | faddr;
2582}
2583
2584static uint32_t *
2584qla4_8xxx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
2585qla4_82xx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr,
2585 uint32_t faddr, uint32_t length)
2586{
2587 uint32_t i;
2588 uint32_t val;
2589 int loops = 0;
2586 uint32_t faddr, uint32_t length)
2587{
2588 uint32_t i;
2589 uint32_t val;
2590 int loops = 0;
2590 while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) {
2591 while ((qla4_82xx_rom_lock(ha) != 0) && (loops < 50000)) {
2591 udelay(100);
2592 cond_resched();
2593 loops++;
2594 }
2595 if (loops >= 50000) {
2596 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
2597 return dwptr;
2598 }
2599
2600 /* Dword reads to flash. */
2601 for (i = 0; i < length/4; i++, faddr += 4) {
2592 udelay(100);
2593 cond_resched();
2594 loops++;
2595 }
2596 if (loops >= 50000) {
2597 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n");
2598 return dwptr;
2599 }
2600
2601 /* Dword reads to flash. */
2602 for (i = 0; i < length/4; i++, faddr += 4) {
2602 if (qla4_8xxx_do_rom_fast_read(ha, faddr, &val)) {
2603 if (qla4_82xx_do_rom_fast_read(ha, faddr, &val)) {
2603 ql4_printk(KERN_WARNING, ha,
2604 "Do ROM fast read failed\n");
2605 goto done_read;
2606 }
2607 dwptr[i] = __constant_cpu_to_le32(val);
2608 }
2609
2610done_read:
2604 ql4_printk(KERN_WARNING, ha,
2605 "Do ROM fast read failed\n");
2606 goto done_read;
2607 }
2608 dwptr[i] = __constant_cpu_to_le32(val);
2609 }
2610
2611done_read:
2611 qla4_8xxx_rom_unlock(ha);
2612 qla4_82xx_rom_unlock(ha);
2612 return dwptr;
2613}
2614
2615/**
2616 * Address and length are byte address
2617 **/
2618static uint8_t *
2613 return dwptr;
2614}
2615
2616/**
2617 * Address and length are byte address
2618 **/
2619static uint8_t *
2619qla4_8xxx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
2620qla4_82xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
2620 uint32_t offset, uint32_t length)
2621{
2621 uint32_t offset, uint32_t length)
2622{
2622 qla4_8xxx_read_flash_data(ha, (uint32_t *)buf, offset, length);
2623 qla4_82xx_read_flash_data(ha, (uint32_t *)buf, offset, length);
2623 return buf;
2624}
2625
2626static int
2627qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
2628{
2629 const char *loc, *locations[] = { "DEF", "PCI" };
2630

--- 19 unchanged lines hidden (view full) ---

2650 struct qla_flt_header *flt;
2651 struct qla_flt_region *region;
2652 struct ql82xx_hw_data *hw = &ha->hw;
2653
2654 hw->flt_region_flt = flt_addr;
2655 wptr = (uint16_t *)ha->request_ring;
2656 flt = (struct qla_flt_header *)ha->request_ring;
2657 region = (struct qla_flt_region *)&flt[1];
2624 return buf;
2625}
2626
2627static int
2628qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start)
2629{
2630 const char *loc, *locations[] = { "DEF", "PCI" };
2631

--- 19 unchanged lines hidden (view full) ---

2651 struct qla_flt_header *flt;
2652 struct qla_flt_region *region;
2653 struct ql82xx_hw_data *hw = &ha->hw;
2654
2655 hw->flt_region_flt = flt_addr;
2656 wptr = (uint16_t *)ha->request_ring;
2657 flt = (struct qla_flt_header *)ha->request_ring;
2658 region = (struct qla_flt_region *)&flt[1];
2658 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2659 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2659 flt_addr << 2, OPTROM_BURST_SIZE);
2660 if (*wptr == __constant_cpu_to_le16(0xffff))
2661 goto no_flash_data;
2662 if (flt->version != __constant_cpu_to_le16(1)) {
2663 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
2664 "version=0x%x length=0x%x checksum=0x%x.\n",
2665 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
2666 le16_to_cpu(flt->checksum)));

--- 60 unchanged lines hidden (view full) ---

2727done:
2728 DEBUG2(ql4_printk(KERN_INFO, ha, "FLT[%s]: flt=0x%x fdt=0x%x "
2729 "boot=0x%x bootload=0x%x fw=0x%x\n", loc, hw->flt_region_flt,
2730 hw->flt_region_fdt, hw->flt_region_boot, hw->flt_region_bootload,
2731 hw->flt_region_fw));
2732}
2733
2734static void
2660 flt_addr << 2, OPTROM_BURST_SIZE);
2661 if (*wptr == __constant_cpu_to_le16(0xffff))
2662 goto no_flash_data;
2663 if (flt->version != __constant_cpu_to_le16(1)) {
2664 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: "
2665 "version=0x%x length=0x%x checksum=0x%x.\n",
2666 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
2667 le16_to_cpu(flt->checksum)));

--- 60 unchanged lines hidden (view full) ---

2728done:
2729 DEBUG2(ql4_printk(KERN_INFO, ha, "FLT[%s]: flt=0x%x fdt=0x%x "
2730 "boot=0x%x bootload=0x%x fw=0x%x\n", loc, hw->flt_region_flt,
2731 hw->flt_region_fdt, hw->flt_region_boot, hw->flt_region_bootload,
2732 hw->flt_region_fw));
2733}
2734
2735static void
2735qla4_8xxx_get_fdt_info(struct scsi_qla_host *ha)
2736qla4_82xx_get_fdt_info(struct scsi_qla_host *ha)
2736{
2737#define FLASH_BLK_SIZE_4K 0x1000
2738#define FLASH_BLK_SIZE_32K 0x8000
2739#define FLASH_BLK_SIZE_64K 0x10000
2740 const char *loc, *locations[] = { "MID", "FDT" };
2741 uint16_t cnt, chksum;
2742 uint16_t *wptr;
2743 struct qla_fdt_layout *fdt;
2744 uint16_t mid = 0;
2745 uint16_t fid = 0;
2746 struct ql82xx_hw_data *hw = &ha->hw;
2747
2748 hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2749 hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
2750
2751 wptr = (uint16_t *)ha->request_ring;
2752 fdt = (struct qla_fdt_layout *)ha->request_ring;
2737{
2738#define FLASH_BLK_SIZE_4K 0x1000
2739#define FLASH_BLK_SIZE_32K 0x8000
2740#define FLASH_BLK_SIZE_64K 0x10000
2741 const char *loc, *locations[] = { "MID", "FDT" };
2742 uint16_t cnt, chksum;
2743 uint16_t *wptr;
2744 struct qla_fdt_layout *fdt;
2745 uint16_t mid = 0;
2746 uint16_t fid = 0;
2747 struct ql82xx_hw_data *hw = &ha->hw;
2748
2749 hw->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2750 hw->flash_data_off = FARX_ACCESS_FLASH_DATA;
2751
2752 wptr = (uint16_t *)ha->request_ring;
2753 fdt = (struct qla_fdt_layout *)ha->request_ring;
2753 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2754 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2754 hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
2755
2756 if (*wptr == __constant_cpu_to_le16(0xffff))
2757 goto no_flash_data;
2758
2759 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
2760 fdt->sig[3] != 'D')
2761 goto no_flash_data;

--- 32 unchanged lines hidden (view full) ---

2794 DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
2795 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
2796 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
2797 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
2798 hw->fdt_block_size));
2799}
2800
2801static void
2755 hw->flt_region_fdt << 2, OPTROM_BURST_SIZE);
2756
2757 if (*wptr == __constant_cpu_to_le16(0xffff))
2758 goto no_flash_data;
2759
2760 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
2761 fdt->sig[3] != 'D')
2762 goto no_flash_data;

--- 32 unchanged lines hidden (view full) ---

2795 DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
2796 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
2797 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd,
2798 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable,
2799 hw->fdt_block_size));
2800}
2801
2802static void
2802qla4_8xxx_get_idc_param(struct scsi_qla_host *ha)
2803qla4_82xx_get_idc_param(struct scsi_qla_host *ha)
2803{
2804#define QLA82XX_IDC_PARAM_ADDR 0x003e885c
2805 uint32_t *wptr;
2806
2807 if (!is_qla8022(ha))
2808 return;
2809 wptr = (uint32_t *)ha->request_ring;
2804{
2805#define QLA82XX_IDC_PARAM_ADDR 0x003e885c
2806 uint32_t *wptr;
2807
2808 if (!is_qla8022(ha))
2809 return;
2810 wptr = (uint32_t *)ha->request_ring;
2810 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2811 qla4_82xx_read_optrom_data(ha, (uint8_t *)ha->request_ring,
2811 QLA82XX_IDC_PARAM_ADDR , 8);
2812
2813 if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
2814 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
2815 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
2816 } else {
2817 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
2818 ha->nx_reset_timeout = le32_to_cpu(*wptr);

--- 12 unchanged lines hidden (view full) ---

2831 int ret;
2832 uint32_t flt_addr;
2833
2834 ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
2835 if (ret != QLA_SUCCESS)
2836 return ret;
2837
2838 qla4_8xxx_get_flt_info(ha, flt_addr);
2812 QLA82XX_IDC_PARAM_ADDR , 8);
2813
2814 if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
2815 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT;
2816 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT;
2817 } else {
2818 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++);
2819 ha->nx_reset_timeout = le32_to_cpu(*wptr);

--- 12 unchanged lines hidden (view full) ---

2832 int ret;
2833 uint32_t flt_addr;
2834
2835 ret = qla4_8xxx_find_flt_start(ha, &flt_addr);
2836 if (ret != QLA_SUCCESS)
2837 return ret;
2838
2839 qla4_8xxx_get_flt_info(ha, flt_addr);
2839 qla4_8xxx_get_fdt_info(ha);
2840 qla4_8xxx_get_idc_param(ha);
2840 qla4_82xx_get_fdt_info(ha);
2841 qla4_82xx_get_idc_param(ha);
2841
2842 return QLA_SUCCESS;
2843}
2844
2845/**
2846 * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
2847 * @ha: pointer to host adapter structure.
2848 *

--- 17 unchanged lines hidden (view full) ---

2866 &mbox_cmd[0], &mbox_sts[0]);
2867
2868 DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
2869 __func__, status));
2870 return status;
2871}
2872
2873/**
2842
2843 return QLA_SUCCESS;
2844}
2845
2846/**
2847 * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance
2848 * @ha: pointer to host adapter structure.
2849 *

--- 17 unchanged lines hidden (view full) ---

2867 &mbox_cmd[0], &mbox_sts[0]);
2868
2869 DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no,
2870 __func__, status));
2871 return status;
2872}
2873
2874/**
2874 * qla4_8xxx_isp_reset - Resets ISP and aborts all outstanding commands.
2875 * qla4_82xx_isp_reset - Resets ISP and aborts all outstanding commands.
2875 * @ha: pointer to host adapter structure.
2876 **/
2877int
2876 * @ha: pointer to host adapter structure.
2877 **/
2878int
2878qla4_8xxx_isp_reset(struct scsi_qla_host *ha)
2879qla4_82xx_isp_reset(struct scsi_qla_host *ha)
2879{
2880 int rval;
2881 uint32_t dev_state;
2882
2880{
2881 int rval;
2882 uint32_t dev_state;
2883
2883 qla4_8xxx_idc_lock(ha);
2884 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2884 qla4_82xx_idc_lock(ha);
2885 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2885
2886 if (dev_state == QLA82XX_DEV_READY) {
2887 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
2886
2887 if (dev_state == QLA82XX_DEV_READY) {
2888 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n");
2888 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2889 qla4_82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2889 QLA82XX_DEV_NEED_RESET);
2890 set_bit(AF_82XX_RST_OWNER, &ha->flags);
2891 } else
2892 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
2893
2890 QLA82XX_DEV_NEED_RESET);
2891 set_bit(AF_82XX_RST_OWNER, &ha->flags);
2892 } else
2893 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n");
2894
2894 qla4_8xxx_idc_unlock(ha);
2895 qla4_82xx_idc_unlock(ha);
2895
2896 rval = qla4_8xxx_device_state_handler(ha);
2897
2896
2897 rval = qla4_8xxx_device_state_handler(ha);
2898
2898 qla4_8xxx_idc_lock(ha);
2899 qla4_82xx_idc_lock(ha);
2899 qla4_8xxx_clear_rst_ready(ha);
2900 qla4_8xxx_clear_rst_ready(ha);
2900 qla4_8xxx_idc_unlock(ha);
2901 qla4_82xx_idc_unlock(ha);
2901
2902 if (rval == QLA_SUCCESS) {
2902
2903 if (rval == QLA_SUCCESS) {
2903 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_8xxx_isp_reset\n");
2904 ql4_printk(KERN_INFO, ha, "Clearing AF_RECOVERY in qla4_82xx_isp_reset\n");
2904 clear_bit(AF_FW_RECOVERY, &ha->flags);
2905 }
2906
2907 return rval;
2908}
2909
2910/**
2911 * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number

--- 110 unchanged lines hidden (view full) ---

3022 __func__, mbox_sts[0]));
3023 return QLA_ERROR;
3024 }
3025
3026 return QLA_SUCCESS;
3027}
3028
3029void
2905 clear_bit(AF_FW_RECOVERY, &ha->flags);
2906 }
2907
2908 return rval;
2909}
2910
2911/**
2912 * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number

--- 110 unchanged lines hidden (view full) ---

3023 __func__, mbox_sts[0]));
3024 return QLA_ERROR;
3025 }
3026
3027 return QLA_SUCCESS;
3028}
3029
3030void
3030qla4_8xxx_enable_intrs(struct scsi_qla_host *ha)
3031qla4_82xx_enable_intrs(struct scsi_qla_host *ha)
3031{
3032 qla4_8xxx_mbx_intr_enable(ha);
3033
3034 spin_lock_irq(&ha->hardware_lock);
3035 /* BIT 10 - reset */
3032{
3033 qla4_8xxx_mbx_intr_enable(ha);
3034
3035 spin_lock_irq(&ha->hardware_lock);
3036 /* BIT 10 - reset */
3036 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
3037 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
3037 spin_unlock_irq(&ha->hardware_lock);
3038 set_bit(AF_INTERRUPTS_ON, &ha->flags);
3039}
3040
3041void
3038 spin_unlock_irq(&ha->hardware_lock);
3039 set_bit(AF_INTERRUPTS_ON, &ha->flags);
3040}
3041
3042void
3042qla4_8xxx_disable_intrs(struct scsi_qla_host *ha)
3043qla4_82xx_disable_intrs(struct scsi_qla_host *ha)
3043{
3044 if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
3045 qla4_8xxx_mbx_intr_disable(ha);
3046
3047 spin_lock_irq(&ha->hardware_lock);
3048 /* BIT 10 - set */
3044{
3045 if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
3046 qla4_8xxx_mbx_intr_disable(ha);
3047
3048 spin_lock_irq(&ha->hardware_lock);
3049 /* BIT 10 - set */
3049 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
3050 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
3050 spin_unlock_irq(&ha->hardware_lock);
3051}
3052
3053struct ql4_init_msix_entry {
3054 uint16_t entry;
3055 uint16_t index;
3056 const char *name;
3057 irq_handler_t handler;

--- 69 unchanged lines hidden --- 		3051 spin_unlock_irq(&ha->hardware_lock);
3052}
3053
3054struct ql4_init_msix_entry {
3055 uint16_t entry;
3056 uint16_t index;
3057 const char *name;
3058 irq_handler_t handler;

--- 69 unchanged lines hidden ---