ql4_mbx.c (d46bdeb14447f0b7e4420c7b1525c8ad9f64ed1b) ql4_mbx.c (f8086f4fd462195a5a824c851997bd12ffceae00)
1/*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8#include "ql4_def.h"

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80 if (is_qla8022(ha)) {
81 if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
82 DEBUG2(ql4_printk(KERN_WARNING, ha,
83 "scsi%ld: %s: prematurely completing mbx cmd as firmware recovery detected\n",
84 ha->host_no, __func__));
85 goto mbox_exit;
86 }
87 /* Do not send any mbx cmd if h/w is in failed state*/
1/*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8#include "ql4_def.h"

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80 if (is_qla8022(ha)) {
81 if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
82 DEBUG2(ql4_printk(KERN_WARNING, ha,
83 "scsi%ld: %s: prematurely completing mbx cmd as firmware recovery detected\n",
84 ha->host_no, __func__));
85 goto mbox_exit;
86 }
87 /* Do not send any mbx cmd if h/w is in failed state*/
88 qla4_8xxx_idc_lock(ha);
89 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
90 qla4_8xxx_idc_unlock(ha);
88 qla4_82xx_idc_lock(ha);
89 dev_state = qla4_82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
90 qla4_82xx_idc_unlock(ha);
91 if (dev_state == QLA82XX_DEV_FAILED) {
92 ql4_printk(KERN_WARNING, ha,
93 "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
94 ha->host_no, __func__);
95 goto mbox_exit;
96 }
97 }
98

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175 intr_status =
176 readl(&ha->qla4_8xxx_reg->host_status);
177 ha->isp_ops->interrupt_service_routine(
178 ha, intr_status);
179 if (test_bit(AF_INTERRUPTS_ON,
180 &ha->flags) &&
181 test_bit(AF_INTx_ENABLED,
182 &ha->flags))
91 if (dev_state == QLA82XX_DEV_FAILED) {
92 ql4_printk(KERN_WARNING, ha,
93 "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
94 ha->host_no, __func__);
95 goto mbox_exit;
96 }
97 }
98

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175 intr_status =
176 readl(&ha->qla4_8xxx_reg->host_status);
177 ha->isp_ops->interrupt_service_routine(
178 ha, intr_status);
179 if (test_bit(AF_INTERRUPTS_ON,
180 &ha->flags) &&
181 test_bit(AF_INTx_ENABLED,
182 &ha->flags))
183 qla4_8xxx_wr_32(ha,
183 qla4_82xx_wr_32(ha,
184 ha->nx_legacy_intr.tgt_mask_reg,
185 0xfbff);
186 }
187 } else {
188 intr_status = readl(&ha->reg->ctrl_status);
189 if (intr_status & INTR_PENDING) {
190 /*
191 * Service the interrupt.

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217 " Scheduling Adapter Reset\n", ha->host_no,
218 mbx_cmd[0]));
219 ha->mailbox_timeout_count++;
220 mbx_sts[0] = (-1);
221 set_bit(DPC_RESET_HA, &ha->dpc_flags);
222 if (is_qla8022(ha)) {
223 ql4_printk(KERN_INFO, ha,
224 "disabling pause transmit on port 0 & 1.\n");
184 ha->nx_legacy_intr.tgt_mask_reg,
185 0xfbff);
186 }
187 } else {
188 intr_status = readl(&ha->reg->ctrl_status);
189 if (intr_status & INTR_PENDING) {
190 /*
191 * Service the interrupt.

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217 " Scheduling Adapter Reset\n", ha->host_no,
218 mbx_cmd[0]));
219 ha->mailbox_timeout_count++;
220 mbx_sts[0] = (-1);
221 set_bit(DPC_RESET_HA, &ha->dpc_flags);
222 if (is_qla8022(ha)) {
223 ql4_printk(KERN_INFO, ha,
224 "disabling pause transmit on port 0 & 1.\n");
225 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
225 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
226 CRB_NIU_XG_PAUSE_CTL_P0 |
227 CRB_NIU_XG_PAUSE_CTL_P1);
228 }
229 goto mbox_exit;
230 }
231
232 /*
233 * Copy the mailbox out registers to the caller's mailbox in/out

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368static uint8_t
369qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
370 uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
371{
372 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
373 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
374
375 if (is_qla8022(ha))
226 CRB_NIU_XG_PAUSE_CTL_P0 |
227 CRB_NIU_XG_PAUSE_CTL_P1);
228 }
229 goto mbox_exit;
230 }
231
232 /*
233 * Copy the mailbox out registers to the caller's mailbox in/out

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368static uint8_t
369qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
370 uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
371{
372 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
373 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
374
375 if (is_qla8022(ha))
376 qla4_8xxx_wr_32(ha, ha->nx_db_wr_ptr, 0);
376 qla4_82xx_wr_32(ha, ha->nx_db_wr_ptr, 0);
377
378 mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
379 mbox_cmd[1] = 0;
380 mbox_cmd[2] = LSDW(init_fw_cb_dma);
381 mbox_cmd[3] = MSDW(init_fw_cb_dma);
382 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
383 mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
384

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378 mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
379 mbox_cmd[1] = 0;
380 mbox_cmd[2] = LSDW(init_fw_cb_dma);
381 mbox_cmd[3] = MSDW(init_fw_cb_dma);
382 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
383 mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
384

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