ql4_isr.c (24c14200947d0c2ca6943fe0353438c3ac9c1c2a) ql4_isr.c (f8086f4fd462195a5a824c851997bd12ffceae00)
1/*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8#include "ql4_def.h"

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811 DEBUG2(printk("scsi%ld: Unknown mailbox status %08X\n",
812 ha->host_no, mbox_status));
813
814 ha->mbox_status[0] = mbox_status;
815 }
816}
817
818/**
1/*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8#include "ql4_def.h"

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811 DEBUG2(printk("scsi%ld: Unknown mailbox status %08X\n",
812 ha->host_no, mbox_status));
813
814 ha->mbox_status[0] = mbox_status;
815 }
816}
817
818/**
819 * qla4_8xxx_interrupt_service_routine - isr
819 * qla4_82xx_interrupt_service_routine - isr
820 * @ha: pointer to host adapter structure.
821 *
822 * This is the main interrupt service routine.
823 * hardware_lock locked upon entry. runs in interrupt context.
824 **/
820 * @ha: pointer to host adapter structure.
821 *
822 * This is the main interrupt service routine.
823 * hardware_lock locked upon entry. runs in interrupt context.
824 **/
825void qla4_8xxx_interrupt_service_routine(struct scsi_qla_host *ha,
825void qla4_82xx_interrupt_service_routine(struct scsi_qla_host *ha,
826 uint32_t intr_status)
827{
828 /* Process response queue interrupt. */
829 if (intr_status & HSRX_RISC_IOCB_INT)
830 qla4xxx_process_response_queue(ha);
831
832 /* Process mailbox/asynch event interrupt.*/
833 if (intr_status & HSRX_RISC_MB_INT)

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861 /* Clear Mailbox Interrupt */
862 writel(set_rmask(CSR_SCSI_PROCESSOR_INTR),
863 &ha->reg->ctrl_status);
864 readl(&ha->reg->ctrl_status);
865 }
866}
867
868/**
826 uint32_t intr_status)
827{
828 /* Process response queue interrupt. */
829 if (intr_status & HSRX_RISC_IOCB_INT)
830 qla4xxx_process_response_queue(ha);
831
832 /* Process mailbox/asynch event interrupt.*/
833 if (intr_status & HSRX_RISC_MB_INT)

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861 /* Clear Mailbox Interrupt */
862 writel(set_rmask(CSR_SCSI_PROCESSOR_INTR),
863 &ha->reg->ctrl_status);
864 readl(&ha->reg->ctrl_status);
865 }
866}
867
868/**
869 * qla4_8xxx_spurious_interrupt - processes spurious interrupt
869 * qla4_82xx_spurious_interrupt - processes spurious interrupt
870 * @ha: pointer to host adapter structure.
871 * @reqs_count: .
872 *
873 **/
870 * @ha: pointer to host adapter structure.
871 * @reqs_count: .
872 *
873 **/
874static void qla4_8xxx_spurious_interrupt(struct scsi_qla_host *ha,
874static void qla4_82xx_spurious_interrupt(struct scsi_qla_host *ha,
875 uint8_t reqs_count)
876{
877 if (reqs_count)
878 return;
879
880 DEBUG2(ql4_printk(KERN_INFO, ha, "Spurious Interrupt\n"));
881 if (is_qla8022(ha)) {
882 writel(0, &ha->qla4_8xxx_reg->host_int);
883 if (test_bit(AF_INTx_ENABLED, &ha->flags))
875 uint8_t reqs_count)
876{
877 if (reqs_count)
878 return;
879
880 DEBUG2(ql4_printk(KERN_INFO, ha, "Spurious Interrupt\n"));
881 if (is_qla8022(ha)) {
882 writel(0, &ha->qla4_8xxx_reg->host_int);
883 if (test_bit(AF_INTx_ENABLED, &ha->flags))
884 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
884 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg,
885 0xfbff);
886 }
887 ha->spurious_int_count++;
888}
889
890/**
891 * qla4xxx_intr_handler - hardware interrupt handler.
892 * @irq: Unused

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979 }
980
981 spin_unlock_irqrestore(&ha->hardware_lock, flags);
982
983 return IRQ_HANDLED;
984}
985
986/**
885 0xfbff);
886 }
887 ha->spurious_int_count++;
888}
889
890/**
891 * qla4xxx_intr_handler - hardware interrupt handler.
892 * @irq: Unused

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979 }
980
981 spin_unlock_irqrestore(&ha->hardware_lock, flags);
982
983 return IRQ_HANDLED;
984}
985
986/**
987 * qla4_8xxx_intr_handler - hardware interrupt handler.
987 * qla4_82xx_intr_handler - hardware interrupt handler.
988 * @irq: Unused
989 * @dev_id: Pointer to host adapter structure
990 **/
988 * @irq: Unused
989 * @dev_id: Pointer to host adapter structure
990 **/
991irqreturn_t qla4_8xxx_intr_handler(int irq, void *dev_id)
991irqreturn_t qla4_82xx_intr_handler(int irq, void *dev_id)
992{
993 struct scsi_qla_host *ha = dev_id;
994 uint32_t intr_status;
995 uint32_t status;
996 unsigned long flags = 0;
997 uint8_t reqs_count = 0;
998
999 if (unlikely(pci_channel_offline(ha->pdev)))
1000 return IRQ_HANDLED;
1001
1002 ha->isr_count++;
992{
993 struct scsi_qla_host *ha = dev_id;
994 uint32_t intr_status;
995 uint32_t status;
996 unsigned long flags = 0;
997 uint8_t reqs_count = 0;
998
999 if (unlikely(pci_channel_offline(ha->pdev)))
1000 return IRQ_HANDLED;
1001
1002 ha->isr_count++;
1003 status = qla4_8xxx_rd_32(ha, ISR_INT_VECTOR);
1003 status = qla4_82xx_rd_32(ha, ISR_INT_VECTOR);
1004 if (!(status & ha->nx_legacy_intr.int_vec_bit))
1005 return IRQ_NONE;
1006
1004 if (!(status & ha->nx_legacy_intr.int_vec_bit))
1005 return IRQ_NONE;
1006
1007 status = qla4_8xxx_rd_32(ha, ISR_INT_STATE_REG);
1007 status = qla4_82xx_rd_32(ha, ISR_INT_STATE_REG);
1008 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status)) {
1009 DEBUG2(ql4_printk(KERN_INFO, ha,
1010 "%s legacy Int not triggered\n", __func__));
1011 return IRQ_NONE;
1012 }
1013
1014 /* clear the interrupt */
1008 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status)) {
1009 DEBUG2(ql4_printk(KERN_INFO, ha,
1010 "%s legacy Int not triggered\n", __func__));
1011 return IRQ_NONE;
1012 }
1013
1014 /* clear the interrupt */
1015 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
1015 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
1016
1017 /* read twice to ensure write is flushed */
1016
1017 /* read twice to ensure write is flushed */
1018 qla4_8xxx_rd_32(ha, ISR_INT_VECTOR);
1019 qla4_8xxx_rd_32(ha, ISR_INT_VECTOR);
1018 qla4_82xx_rd_32(ha, ISR_INT_VECTOR);
1019 qla4_82xx_rd_32(ha, ISR_INT_VECTOR);
1020
1021 spin_lock_irqsave(&ha->hardware_lock, flags);
1022 while (1) {
1023 if (!(readl(&ha->qla4_8xxx_reg->host_int) &
1024 ISRX_82XX_RISC_INT)) {
1020
1021 spin_lock_irqsave(&ha->hardware_lock, flags);
1022 while (1) {
1023 if (!(readl(&ha->qla4_8xxx_reg->host_int) &
1024 ISRX_82XX_RISC_INT)) {
1025 qla4_8xxx_spurious_interrupt(ha, reqs_count);
1025 qla4_82xx_spurious_interrupt(ha, reqs_count);
1026 break;
1027 }
1028 intr_status = readl(&ha->qla4_8xxx_reg->host_status);
1029 if ((intr_status &
1030 (HSRX_RISC_MB_INT | HSRX_RISC_IOCB_INT)) == 0) {
1026 break;
1027 }
1028 intr_status = readl(&ha->qla4_8xxx_reg->host_status);
1029 if ((intr_status &
1030 (HSRX_RISC_MB_INT | HSRX_RISC_IOCB_INT)) == 0) {
1031 qla4_8xxx_spurious_interrupt(ha, reqs_count);
1031 qla4_82xx_spurious_interrupt(ha, reqs_count);
1032 break;
1033 }
1034
1035 ha->isp_ops->interrupt_service_routine(ha, intr_status);
1036
1037 /* Enable Interrupt */
1032 break;
1033 }
1034
1035 ha->isp_ops->interrupt_service_routine(ha, intr_status);
1036
1037 /* Enable Interrupt */
1038 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
1038 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
1039
1040 if (++reqs_count == MAX_REQS_SERVICED_PER_INTR)
1041 break;
1042 }
1043
1044 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1045 return IRQ_HANDLED;
1046}

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1054 if (!ha) {
1055 DEBUG2(printk(KERN_INFO
1056 "qla4xxx: MSIX: Interrupt with NULL host ptr\n"));
1057 return IRQ_NONE;
1058 }
1059
1060 ha->isr_count++;
1061 /* clear the interrupt */
1039
1040 if (++reqs_count == MAX_REQS_SERVICED_PER_INTR)
1041 break;
1042 }
1043
1044 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1045 return IRQ_HANDLED;
1046}

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1054 if (!ha) {
1055 DEBUG2(printk(KERN_INFO
1056 "qla4xxx: MSIX: Interrupt with NULL host ptr\n"));
1057 return IRQ_NONE;
1058 }
1059
1060 ha->isr_count++;
1061 /* clear the interrupt */
1062 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
1062 qla4_82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
1063
1064 /* read twice to ensure write is flushed */
1063
1064 /* read twice to ensure write is flushed */
1065 qla4_8xxx_rd_32(ha, ISR_INT_VECTOR);
1066 qla4_8xxx_rd_32(ha, ISR_INT_VECTOR);
1065 qla4_82xx_rd_32(ha, ISR_INT_VECTOR);
1066 qla4_82xx_rd_32(ha, ISR_INT_VECTOR);
1067
1068 return qla4_8xxx_default_intr_handler(irq, dev_id);
1069}
1070
1071/**
1072 * qla4_8xxx_default_intr_handler - hardware interrupt handler.
1073 * @irq: Unused
1074 * @dev_id: Pointer to host adapter structure

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1083 unsigned long flags;
1084 uint32_t intr_status;
1085 uint8_t reqs_count = 0;
1086
1087 spin_lock_irqsave(&ha->hardware_lock, flags);
1088 while (1) {
1089 if (!(readl(&ha->qla4_8xxx_reg->host_int) &
1090 ISRX_82XX_RISC_INT)) {
1067
1068 return qla4_8xxx_default_intr_handler(irq, dev_id);
1069}
1070
1071/**
1072 * qla4_8xxx_default_intr_handler - hardware interrupt handler.
1073 * @irq: Unused
1074 * @dev_id: Pointer to host adapter structure

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1083 unsigned long flags;
1084 uint32_t intr_status;
1085 uint8_t reqs_count = 0;
1086
1087 spin_lock_irqsave(&ha->hardware_lock, flags);
1088 while (1) {
1089 if (!(readl(&ha->qla4_8xxx_reg->host_int) &
1090 ISRX_82XX_RISC_INT)) {
1091 qla4_8xxx_spurious_interrupt(ha, reqs_count);
1091 qla4_82xx_spurious_interrupt(ha, reqs_count);
1092 break;
1093 }
1094
1095 intr_status = readl(&ha->qla4_8xxx_reg->host_status);
1096 if ((intr_status &
1097 (HSRX_RISC_MB_INT | HSRX_RISC_IOCB_INT)) == 0) {
1092 break;
1093 }
1094
1095 intr_status = readl(&ha->qla4_8xxx_reg->host_status);
1096 if ((intr_status &
1097 (HSRX_RISC_MB_INT | HSRX_RISC_IOCB_INT)) == 0) {
1098 qla4_8xxx_spurious_interrupt(ha, reqs_count);
1098 qla4_82xx_spurious_interrupt(ha, reqs_count);
1099 break;
1100 }
1101
1102 ha->isp_ops->interrupt_service_routine(ha, intr_status);
1103
1104 if (++reqs_count == MAX_REQS_SERVICED_PER_INTR)
1105 break;
1106 }

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1100 }
1101
1102 ha->isp_ops->interrupt_service_routine(ha, intr_status);
1103
1104 if (++reqs_count == MAX_REQS_SERVICED_PER_INTR)
1105 break;
1106 }

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