lpfc_hw.h (2e0fef85e098f6794956b8b80b111179fbb4cbb7) lpfc_hw.h (ed957684294618602b48f1950b0c9bbcb036583f)
1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2004-2007 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *

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54#define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
55#define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
56#define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
57#define SLI2_IOCB_CMD_R3_ENTRIES 0
58#define SLI2_IOCB_RSP_R3_ENTRIES 0
59#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
60#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
61
1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2004-2007 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *

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54#define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
55#define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
56#define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
57#define SLI2_IOCB_CMD_R3_ENTRIES 0
58#define SLI2_IOCB_RSP_R3_ENTRIES 0
59#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
60#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
61
62#define SLI2_IOCB_CMD_SIZE 32
63#define SLI2_IOCB_RSP_SIZE 32
64#define SLI3_IOCB_CMD_SIZE 128
65#define SLI3_IOCB_RSP_SIZE 64
66
62/* Common Transport structures and definitions */
63
64union CtRevisionId {
65 /* Structure is in Big Endian format */
66 struct {
67 uint32_t Revision:8;
68 uint32_t InId:24;
69 } bits;

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1250#define MBX_RUN_PROGRAM 0x1E
1251#define MBX_SET_MASK 0x20
1252#define MBX_SET_SLIM 0x21
1253#define MBX_UNREG_D_ID 0x23
1254#define MBX_KILL_BOARD 0x24
1255#define MBX_CONFIG_FARP 0x25
1256#define MBX_BEACON 0x2A
1257
67/* Common Transport structures and definitions */
68
69union CtRevisionId {
70 /* Structure is in Big Endian format */
71 struct {
72 uint32_t Revision:8;
73 uint32_t InId:24;
74 } bits;

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1255#define MBX_RUN_PROGRAM 0x1E
1256#define MBX_SET_MASK 0x20
1257#define MBX_SET_SLIM 0x21
1258#define MBX_UNREG_D_ID 0x23
1259#define MBX_KILL_BOARD 0x24
1260#define MBX_CONFIG_FARP 0x25
1261#define MBX_BEACON 0x2A
1262
1263#define MBX_CONFIG_HBQ 0x7C
1258#define MBX_LOAD_AREA 0x81
1259#define MBX_RUN_BIU_DIAG64 0x84
1260#define MBX_CONFIG_PORT 0x88
1261#define MBX_READ_SPARM64 0x8D
1262#define MBX_READ_RPI64 0x8F
1263#define MBX_REG_LOGIN64 0x93
1264#define MBX_READ_LA64 0x95
1265

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1329#define CMD_FCP_IREAD64_CR 0x9A
1330#define CMD_FCP_IREAD64_CX 0x9B
1331#define CMD_FCP_ICMND64_CR 0x9C
1332#define CMD_FCP_ICMND64_CX 0x9D
1333#define CMD_FCP_TSEND64_CX 0x9F
1334#define CMD_FCP_TRECEIVE64_CX 0xA1
1335#define CMD_FCP_TRSP64_CX 0xA3
1336
1264#define MBX_LOAD_AREA 0x81
1265#define MBX_RUN_BIU_DIAG64 0x84
1266#define MBX_CONFIG_PORT 0x88
1267#define MBX_READ_SPARM64 0x8D
1268#define MBX_READ_RPI64 0x8F
1269#define MBX_REG_LOGIN64 0x93
1270#define MBX_READ_LA64 0x95
1271

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1335#define CMD_FCP_IREAD64_CR 0x9A
1336#define CMD_FCP_IREAD64_CX 0x9B
1337#define CMD_FCP_ICMND64_CR 0x9C
1338#define CMD_FCP_ICMND64_CX 0x9D
1339#define CMD_FCP_TSEND64_CX 0x9F
1340#define CMD_FCP_TRECEIVE64_CX 0xA1
1341#define CMD_FCP_TRSP64_CX 0xA3
1342
1343#define CMD_IOCB_RCV_SEQ64_CX 0xB5
1344#define CMD_IOCB_RCV_ELS64_CX 0xB7
1345#define CMD_IOCB_RCV_CONT64_CX 0xBB
1346
1337#define CMD_GEN_REQUEST64_CR 0xC2
1338#define CMD_GEN_REQUEST64_CX 0xC3
1339
1340#define CMD_MAX_IOCB_CMD 0xE6
1341#define CMD_IOCB_MASK 0xff
1342
1343#define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1344 iocb */

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1555 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1556#endif
1557
1558#define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
1559#define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
1560#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1561#define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1562#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
1347#define CMD_GEN_REQUEST64_CR 0xC2
1348#define CMD_GEN_REQUEST64_CX 0xC3
1349
1350#define CMD_MAX_IOCB_CMD 0xE6
1351#define CMD_IOCB_MASK 0xff
1352
1353#define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1354 iocb */

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1565 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1566#endif
1567
1568#define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
1569#define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
1570#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1571#define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1572#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
1573#define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
1563#define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1564
1565#define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1566#define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
1567#define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
1568
1569 uint32_t link_speed;
1570#define LINK_SPEED_AUTO 0 /* Auto selection */

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1812typedef struct {
1813 uint32_t rsvd1;
1814 uint32_t rsvd2;
1815 union {
1816 struct ulp_bde sp; /* This BDE points to struct serv_parm
1817 structure */
1818 struct ulp_bde64 sp64;
1819 } un;
1574#define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1575
1576#define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1577#define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
1578#define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
1579
1580 uint32_t link_speed;
1581#define LINK_SPEED_AUTO 0 /* Auto selection */

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1823typedef struct {
1824 uint32_t rsvd1;
1825 uint32_t rsvd2;
1826 union {
1827 struct ulp_bde sp; /* This BDE points to struct serv_parm
1828 structure */
1829 struct ulp_bde64 sp64;
1830 } un;
1831#ifdef __BIG_ENDIAN_BITFIELD
1832 uint16_t rsvd3;
1833 uint16_t vpi;
1834#else /* __LITTLE_ENDIAN_BITFIELD */
1835 uint16_t vpi;
1836 uint16_t rsvd3;
1837#endif
1820} READ_SPARM_VAR;
1821
1822/* Structure for MB Command READ_STATUS (14) */
1823
1824typedef struct {
1825#ifdef __BIG_ENDIAN_BITFIELD
1826 uint32_t rsvd1:31;
1827 uint32_t clrCounters:1;

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1912} READ_XRI_VAR;
1913
1914/* Structure for MB Command READ_REV (17) */
1915
1916typedef struct {
1917#ifdef __BIG_ENDIAN_BITFIELD
1918 uint32_t cv:1;
1919 uint32_t rr:1;
1838} READ_SPARM_VAR;
1839
1840/* Structure for MB Command READ_STATUS (14) */
1841
1842typedef struct {
1843#ifdef __BIG_ENDIAN_BITFIELD
1844 uint32_t rsvd1:31;
1845 uint32_t clrCounters:1;

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1930} READ_XRI_VAR;
1931
1932/* Structure for MB Command READ_REV (17) */
1933
1934typedef struct {
1935#ifdef __BIG_ENDIAN_BITFIELD
1936 uint32_t cv:1;
1937 uint32_t rr:1;
1920 uint32_t rsvd1:29;
1938 uint32_t rsvd2:2;
1939 uint32_t v3req:1;
1940 uint32_t v3rsp:1;
1941 uint32_t rsvd1:25;
1921 uint32_t rv:1;
1922#else /* __LITTLE_ENDIAN_BITFIELD */
1923 uint32_t rv:1;
1942 uint32_t rv:1;
1943#else /* __LITTLE_ENDIAN_BITFIELD */
1944 uint32_t rv:1;
1924 uint32_t rsvd1:29;
1945 uint32_t rsvd1:25;
1946 uint32_t v3rsp:1;
1947 uint32_t v3req:1;
1948 uint32_t rsvd2:2;
1925 uint32_t rr:1;
1926 uint32_t cv:1;
1927#endif
1928
1929 uint32_t biuRev;
1930 uint32_t smRev;
1931 union {
1932 uint32_t smFwRev;

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1966
1967 uint32_t postKernRev;
1968 uint32_t opFwRev;
1969 uint8_t opFwName[16];
1970 uint32_t sli1FwRev;
1971 uint8_t sli1FwName[16];
1972 uint32_t sli2FwRev;
1973 uint8_t sli2FwName[16];
1949 uint32_t rr:1;
1950 uint32_t cv:1;
1951#endif
1952
1953 uint32_t biuRev;
1954 uint32_t smRev;
1955 union {
1956 uint32_t smFwRev;

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1990
1991 uint32_t postKernRev;
1992 uint32_t opFwRev;
1993 uint8_t opFwName[16];
1994 uint32_t sli1FwRev;
1995 uint8_t sli1FwName[16];
1996 uint32_t sli2FwRev;
1997 uint8_t sli2FwName[16];
1974 uint32_t rsvd2;
1975 uint32_t RandomData[7];
1998 uint32_t sli3Feat;
1999 uint32_t RandomData[6];
1976} READ_REV_VAR;
1977
1978/* Structure for MB Command READ_LINK_STAT (18) */
1979
1980typedef struct {
1981 uint32_t rsvd1;
1982 uint32_t linkFailureCnt;
1983 uint32_t lossSyncCnt;

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2007 uint32_t rsvd2:8;
2008#endif
2009
2010 union {
2011 struct ulp_bde sp;
2012 struct ulp_bde64 sp64;
2013 } un;
2014
2000} READ_REV_VAR;
2001
2002/* Structure for MB Command READ_LINK_STAT (18) */
2003
2004typedef struct {
2005 uint32_t rsvd1;
2006 uint32_t linkFailureCnt;
2007 uint32_t lossSyncCnt;

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2031 uint32_t rsvd2:8;
2032#endif
2033
2034 union {
2035 struct ulp_bde sp;
2036 struct ulp_bde64 sp64;
2037 } un;
2038
2039#ifdef __BIG_ENDIAN_BITFIELD
2040 uint16_t rsvd6;
2041 uint16_t vpi;
2042#else /* __LITTLE_ENDIAN_BITFIELD */
2043 uint16_t vpi;
2044 uint16_t rsvd6;
2045#endif
2046
2015} REG_LOGIN_VAR;
2016
2017/* Word 30 contents for REG_LOGIN */
2018typedef union {
2019 struct {
2020#ifdef __BIG_ENDIAN_BITFIELD
2021 uint16_t rsvd1:12;
2022 uint16_t wd30_class:4;

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2031} REG_WD30;
2032
2033/* Structure for MB Command UNREG_LOGIN (20) */
2034
2035typedef struct {
2036#ifdef __BIG_ENDIAN_BITFIELD
2037 uint16_t rsvd1;
2038 uint16_t rpi;
2047} REG_LOGIN_VAR;
2048
2049/* Word 30 contents for REG_LOGIN */
2050typedef union {
2051 struct {
2052#ifdef __BIG_ENDIAN_BITFIELD
2053 uint16_t rsvd1:12;
2054 uint16_t wd30_class:4;

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2063} REG_WD30;
2064
2065/* Structure for MB Command UNREG_LOGIN (20) */
2066
2067typedef struct {
2068#ifdef __BIG_ENDIAN_BITFIELD
2069 uint16_t rsvd1;
2070 uint16_t rpi;
2071 uint32_t rsvd2;
2072 uint32_t rsvd3;
2073 uint32_t rsvd4;
2074 uint32_t rsvd5;
2075 uint16_t rsvd6;
2076 uint16_t vpi;
2039#else /* __LITTLE_ENDIAN_BITFIELD */
2040 uint16_t rpi;
2041 uint16_t rsvd1;
2077#else /* __LITTLE_ENDIAN_BITFIELD */
2078 uint16_t rpi;
2079 uint16_t rsvd1;
2080 uint32_t rsvd2;
2081 uint32_t rsvd3;
2082 uint32_t rsvd4;
2083 uint32_t rsvd5;
2084 uint16_t vpi;
2085 uint16_t rsvd6;
2042#endif
2043} UNREG_LOGIN_VAR;
2044
2045/* Structure for MB Command UNREG_D_ID (0x23) */
2046
2047typedef struct {
2048 uint32_t did;
2086#endif
2087} UNREG_LOGIN_VAR;
2088
2089/* Structure for MB Command UNREG_D_ID (0x23) */
2090
2091typedef struct {
2092 uint32_t did;
2093 uint32_t rsvd2;
2094 uint32_t rsvd3;
2095 uint32_t rsvd4;
2096 uint32_t rsvd5;
2097#ifdef __BIG_ENDIAN_BITFIELD
2098 uint16_t rsvd6;
2099 uint16_t vpi;
2100#else
2101 uint16_t vpi;
2102 uint16_t rsvd6;
2103#endif
2049} UNREG_D_ID_VAR;
2050
2051/* Structure for MB Command READ_LA (21) */
2052/* Structure for MB Command READ_LA64 (0x95) */
2053
2054typedef struct {
2055 uint32_t eventTag; /* Event tag */
2056#ifdef __BIG_ENDIAN_BITFIELD

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2172#define DMP_MEM_REG 0x1
2173#define DMP_NV_PARAMS 0x2
2174
2175#define DMP_REGION_VPD 0xe
2176#define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2177#define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2178#define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2179
2104} UNREG_D_ID_VAR;
2105
2106/* Structure for MB Command READ_LA (21) */
2107/* Structure for MB Command READ_LA64 (0x95) */
2108
2109typedef struct {
2110 uint32_t eventTag; /* Event tag */
2111#ifdef __BIG_ENDIAN_BITFIELD

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2227#define DMP_MEM_REG 0x1
2228#define DMP_NV_PARAMS 0x2
2229
2230#define DMP_REGION_VPD 0xe
2231#define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2232#define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2233#define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2234
2235struct hbq_mask {
2236#ifdef __BIG_ENDIAN_BITFIELD
2237 uint8_t tmatch;
2238 uint8_t tmask;
2239 uint8_t rctlmatch;
2240 uint8_t rctlmask;
2241#else /* __LITTLE_ENDIAN */
2242 uint8_t rctlmask;
2243 uint8_t rctlmatch;
2244 uint8_t tmask;
2245 uint8_t tmatch;
2246#endif
2247};
2180
2248
2249
2250/* Structure for MB Command CONFIG_HBQ (7c) */
2251
2252struct config_hbq_var {
2253#ifdef __BIG_ENDIAN_BITFIELD
2254 uint32_t rsvd1 :7;
2255 uint32_t recvNotify :1; /* Receive Notification */
2256 uint32_t numMask :8; /* # Mask Entries */
2257 uint32_t profile :8; /* Selection Profile */
2258 uint32_t rsvd2 :8;
2259#else /* __LITTLE_ENDIAN */
2260 uint32_t rsvd2 :8;
2261 uint32_t profile :8; /* Selection Profile */
2262 uint32_t numMask :8; /* # Mask Entries */
2263 uint32_t recvNotify :1; /* Receive Notification */
2264 uint32_t rsvd1 :7;
2265#endif
2266
2267#ifdef __BIG_ENDIAN_BITFIELD
2268 uint32_t hbqId :16;
2269 uint32_t rsvd3 :12;
2270 uint32_t ringMask :4;
2271#else /* __LITTLE_ENDIAN */
2272 uint32_t ringMask :4;
2273 uint32_t rsvd3 :12;
2274 uint32_t hbqId :16;
2275#endif
2276
2277#ifdef __BIG_ENDIAN_BITFIELD
2278 uint32_t entry_count :16;
2279 uint32_t rsvd4 :8;
2280 uint32_t headerLen :8;
2281#else /* __LITTLE_ENDIAN */
2282 uint32_t headerLen :8;
2283 uint32_t rsvd4 :8;
2284 uint32_t entry_count :16;
2285#endif
2286
2287 uint32_t hbqaddrLow;
2288 uint32_t hbqaddrHigh;
2289
2290#ifdef __BIG_ENDIAN_BITFIELD
2291 uint32_t rsvd5 :31;
2292 uint32_t logEntry :1;
2293#else /* __LITTLE_ENDIAN */
2294 uint32_t logEntry :1;
2295 uint32_t rsvd5 :31;
2296#endif
2297
2298 uint32_t rsvd6; /* w7 */
2299 uint32_t rsvd7; /* w8 */
2300 uint32_t rsvd8; /* w9 */
2301
2302 struct hbq_mask hbqMasks[6];
2303
2304
2305 union {
2306 uint32_t allprofiles[12];
2307
2308 struct {
2309 #ifdef __BIG_ENDIAN_BITFIELD
2310 uint32_t seqlenoff :16;
2311 uint32_t maxlen :16;
2312 #else /* __LITTLE_ENDIAN */
2313 uint32_t maxlen :16;
2314 uint32_t seqlenoff :16;
2315 #endif
2316 #ifdef __BIG_ENDIAN_BITFIELD
2317 uint32_t rsvd1 :28;
2318 uint32_t seqlenbcnt :4;
2319 #else /* __LITTLE_ENDIAN */
2320 uint32_t seqlenbcnt :4;
2321 uint32_t rsvd1 :28;
2322 #endif
2323 uint32_t rsvd[10];
2324 } profile2;
2325
2326 struct {
2327 #ifdef __BIG_ENDIAN_BITFIELD
2328 uint32_t seqlenoff :16;
2329 uint32_t maxlen :16;
2330 #else /* __LITTLE_ENDIAN */
2331 uint32_t maxlen :16;
2332 uint32_t seqlenoff :16;
2333 #endif
2334 #ifdef __BIG_ENDIAN_BITFIELD
2335 uint32_t cmdcodeoff :28;
2336 uint32_t rsvd1 :12;
2337 uint32_t seqlenbcnt :4;
2338 #else /* __LITTLE_ENDIAN */
2339 uint32_t seqlenbcnt :4;
2340 uint32_t rsvd1 :12;
2341 uint32_t cmdcodeoff :28;
2342 #endif
2343 uint32_t cmdmatch[8];
2344
2345 uint32_t rsvd[2];
2346 } profile3;
2347
2348 struct {
2349 #ifdef __BIG_ENDIAN_BITFIELD
2350 uint32_t seqlenoff :16;
2351 uint32_t maxlen :16;
2352 #else /* __LITTLE_ENDIAN */
2353 uint32_t maxlen :16;
2354 uint32_t seqlenoff :16;
2355 #endif
2356 #ifdef __BIG_ENDIAN_BITFIELD
2357 uint32_t cmdcodeoff :28;
2358 uint32_t rsvd1 :12;
2359 uint32_t seqlenbcnt :4;
2360 #else /* __LITTLE_ENDIAN */
2361 uint32_t seqlenbcnt :4;
2362 uint32_t rsvd1 :12;
2363 uint32_t cmdcodeoff :28;
2364 #endif
2365 uint32_t cmdmatch[8];
2366
2367 uint32_t rsvd[2];
2368 } profile5;
2369
2370 } profiles;
2371
2372};
2373
2374
2375
2181/* Structure for MB Command CONFIG_PORT (0x88) */
2182typedef struct {
2376/* Structure for MB Command CONFIG_PORT (0x88) */
2377typedef struct {
2183 uint32_t pcbLen;
2378#ifdef __BIG_ENDIAN_BITFIELD
2379 uint32_t cBE : 1;
2380 uint32_t cET : 1;
2381 uint32_t cHpcb : 1;
2382 uint32_t cMA : 1;
2383 uint32_t sli_mode : 4;
2384 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2385 * config block */
2386#else /* __LITTLE_ENDIAN */
2387 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2388 * config block */
2389 uint32_t sli_mode : 4;
2390 uint32_t cMA : 1;
2391 uint32_t cHpcb : 1;
2392 uint32_t cET : 1;
2393 uint32_t cBE : 1;
2394#endif
2395
2184 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2185 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
2396 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2397 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
2186 uint32_t hbainit[5];
2398 uint32_t hbainit[6];
2399
2400#ifdef __BIG_ENDIAN_BITFIELD
2401 uint32_t rsvd : 24; /* Reserved */
2402 uint32_t cmv : 1; /* Configure Max VPIs */
2403 uint32_t ccrp : 1; /* Config Command Ring Polling */
2404 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2405 uint32_t chbs : 1; /* Cofigure Host Backing store */
2406 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2407 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2408 uint32_t cmx : 1; /* Configure Max XRIs */
2409 uint32_t cmr : 1; /* Configure Max RPIs */
2410#else /* __LITTLE_ENDIAN */
2411 uint32_t cmr : 1; /* Configure Max RPIs */
2412 uint32_t cmx : 1; /* Configure Max XRIs */
2413 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2414 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2415 uint32_t chbs : 1; /* Cofigure Host Backing store */
2416 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2417 uint32_t ccrp : 1; /* Config Command Ring Polling */
2418 uint32_t cmv : 1; /* Configure Max VPIs */
2419 uint32_t rsvd : 24; /* Reserved */
2420#endif
2421#ifdef __BIG_ENDIAN_BITFIELD
2422 uint32_t rsvd2 : 24; /* Reserved */
2423 uint32_t gmv : 1; /* Grant Max VPIs */
2424 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2425 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2426 uint32_t ghbs : 1; /* Grant Host Backing Store */
2427 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2428 uint32_t gerbm : 1; /* Grant ERBM Request */
2429 uint32_t gmx : 1; /* Grant Max XRIs */
2430 uint32_t gmr : 1; /* Grant Max RPIs */
2431#else /* __LITTLE_ENDIAN */
2432 uint32_t gmr : 1; /* Grant Max RPIs */
2433 uint32_t gmx : 1; /* Grant Max XRIs */
2434 uint32_t gerbm : 1; /* Grant ERBM Request */
2435 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2436 uint32_t ghbs : 1; /* Grant Host Backing Store */
2437 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2438 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2439 uint32_t gmv : 1; /* Grant Max VPIs */
2440 uint32_t rsvd2 : 24; /* Reserved */
2441#endif
2442
2443#ifdef __BIG_ENDIAN_BITFIELD
2444 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2445 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2446#else /* __LITTLE_ENDIAN */
2447 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2448 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2449#endif
2450
2451#ifdef __BIG_ENDIAN_BITFIELD
2452 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2453 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */
2454#else /* __LITTLE_ENDIAN */
2455 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */
2456 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2457#endif
2458
2459 uint32_t rsvd4; /* Reserved */
2460
2461#ifdef __BIG_ENDIAN_BITFIELD
2462 uint32_t rsvd5 : 16; /* Reserved */
2463 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2464#else /* __LITTLE_ENDIAN */
2465 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2466 uint32_t rsvd5 : 16; /* Reserved */
2467#endif
2468
2187} CONFIG_PORT_VAR;
2188
2189/* SLI-2 Port Control Block */
2190
2191/* SLIM POINTER */
2192#define SLIMOFF 0x30 /* WORD */
2193
2194typedef struct _SLI2_RDSC {

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2256 uint32_t IPAddress;
2257} CONFIG_FARP_VAR;
2258
2259/* Union of all Mailbox Command types */
2260#define MAILBOX_CMD_WSIZE 32
2261#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
2262
2263typedef union {
2469} CONFIG_PORT_VAR;
2470
2471/* SLI-2 Port Control Block */
2472
2473/* SLIM POINTER */
2474#define SLIMOFF 0x30 /* WORD */
2475
2476typedef struct _SLI2_RDSC {

--- 61 unchanged lines hidden (view full) ---

2538 uint32_t IPAddress;
2539} CONFIG_FARP_VAR;
2540
2541/* Union of all Mailbox Command types */
2542#define MAILBOX_CMD_WSIZE 32
2543#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
2544
2545typedef union {
2264 uint32_t varWords[MAILBOX_CMD_WSIZE - 1];
2265 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
2266 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
2267 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
2546 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
2547 * feature/max ring number
2548 */
2549 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
2550 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
2551 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
2268 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
2269 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
2270 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
2552 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
2553 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
2554 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
2271 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
2272 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
2555 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
2556 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
2273 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
2274 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
2275 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
2276 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
2277 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
2278 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
2557 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
2558 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
2559 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
2560 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
2561 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
2562 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
2279 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
2280 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
2281 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
2282 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
2563 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
2564 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
2565 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
2566 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
2283 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
2284 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
2567 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
2568 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
2285 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */
2569 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */
2286 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
2570 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
2287 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
2288 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
2289 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) NEW_FEATURE */
2290 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
2571 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
2572 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
2573 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
2574 * NEW_FEATURE
2575 */
2576 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
2577 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
2291} MAILVARIANTS;
2292
2293/*
2294 * SLI-2 specific structures
2295 */
2296
2297struct lpfc_hgp {
2298 __le32 cmdPutInx;
2299 __le32 rspGetInx;
2300};
2301
2302struct lpfc_pgp {
2303 __le32 cmdGetInx;
2304 __le32 rspPutInx;
2305};
2306
2578} MAILVARIANTS;
2579
2580/*
2581 * SLI-2 specific structures
2582 */
2583
2584struct lpfc_hgp {
2585 __le32 cmdPutInx;
2586 __le32 rspGetInx;
2587};
2588
2589struct lpfc_pgp {
2590 __le32 cmdGetInx;
2591 __le32 rspPutInx;
2592};
2593
2307typedef struct _SLI2_DESC {
2308 struct lpfc_hgp host[MAX_RINGS];
2594struct sli2_desc {
2309 uint32_t unused1[16];
2595 uint32_t unused1[16];
2596 struct lpfc_hgp host[MAX_RINGS];
2310 struct lpfc_pgp port[MAX_RINGS];
2597 struct lpfc_pgp port[MAX_RINGS];
2311} SLI2_DESC;
2598};
2312
2599
2600struct sli3_desc {
2601 struct lpfc_hgp host[MAX_RINGS];
2602 uint32_t reserved[8];
2603 uint32_t hbq_put[16];
2604};
2605
2606struct sli3_pgp {
2607 struct lpfc_pgp port[MAX_RINGS];
2608 uint32_t hbq_get[16];
2609};
2610
2313typedef union {
2611typedef union {
2314 SLI2_DESC s2;
2612 struct sli2_desc s2;
2613 struct sli3_desc s3;
2614 struct sli3_pgp s3_pgp;
2315} SLI_VAR;
2316
2615} SLI_VAR;
2616
2617
2317typedef struct {
2318#ifdef __BIG_ENDIAN_BITFIELD
2319 uint16_t mbxStatus;
2320 uint8_t mbxCommand;
2321 uint8_t mbxReserved:6;
2322 uint8_t mbxHc:1;
2323 uint8_t mbxOwner:1; /* Low order bit first word */
2324#else /* __LITTLE_ENDIAN_BITFIELD */

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2612
2613/* IOCB Command template for all 64 bit FCP Target commands */
2614typedef struct {
2615 ULP_BDL bdl;
2616 uint32_t fcpt_Offset;
2617 uint32_t fcpt_Length; /* transfer ready for IWRITE */
2618} FCPT_FIELDS64;
2619
2618typedef struct {
2619#ifdef __BIG_ENDIAN_BITFIELD
2620 uint16_t mbxStatus;
2621 uint8_t mbxCommand;
2622 uint8_t mbxReserved:6;
2623 uint8_t mbxHc:1;
2624 uint8_t mbxOwner:1; /* Low order bit first word */
2625#else /* __LITTLE_ENDIAN_BITFIELD */

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2913
2914/* IOCB Command template for all 64 bit FCP Target commands */
2915typedef struct {
2916 ULP_BDL bdl;
2917 uint32_t fcpt_Offset;
2918 uint32_t fcpt_Length; /* transfer ready for IWRITE */
2919} FCPT_FIELDS64;
2920
2921/* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
2922 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
2923
2924struct rcv_sli3 {
2925 uint32_t word8Rsvd;
2926#ifdef __BIG_ENDIAN_BITFIELD
2927 uint16_t vpi;
2928 uint16_t word9Rsvd;
2929#else /* __LITTLE_ENDIAN */
2930 uint16_t word9Rsvd;
2931 uint16_t vpi;
2932#endif
2933 uint32_t word10Rsvd;
2934 uint32_t acc_len; /* accumulated length */
2935 struct ulp_bde64 bde2;
2936};
2937
2620typedef struct _IOCB { /* IOCB structure */
2621 union {
2622 GENERIC_RSP grsp; /* Generic response */
2623 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
2624 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
2625 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
2626 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
2627 A_MXRI64 amxri; /* abort multiple xri command overlay */
2628 GET_RPI getrpi; /* GET_RPI template */
2629 FCPI_FIELDS fcpi; /* FCP Initiator template */
2630 FCPT_FIELDS fcpt; /* FCP target template */
2631
2632 /* SLI-2 structures */
2633
2938typedef struct _IOCB { /* IOCB structure */
2939 union {
2940 GENERIC_RSP grsp; /* Generic response */
2941 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
2942 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
2943 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
2944 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
2945 A_MXRI64 amxri; /* abort multiple xri command overlay */
2946 GET_RPI getrpi; /* GET_RPI template */
2947 FCPI_FIELDS fcpi; /* FCP Initiator template */
2948 FCPT_FIELDS fcpt; /* FCP target template */
2949
2950 /* SLI-2 structures */
2951
2634 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
2635 bde_64s */
2952 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
2953 * bde_64s */
2636 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
2637 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
2638 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
2639 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
2640 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
2641 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
2642
2643 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */

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2688 uint32_t ulpCommand:8;
2689 uint32_t ulpClass:3;
2690 uint32_t ulpIr:1;
2691 uint32_t ulpPU:2;
2692 uint32_t ulpFCP2Rcvy:1;
2693 uint32_t ulpXS:1;
2694 uint32_t ulpTimeout:8;
2695#endif
2954 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
2955 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
2956 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
2957 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
2958 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
2959 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
2960
2961 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */

--- 44 unchanged lines hidden (view full) ---

3006 uint32_t ulpCommand:8;
3007 uint32_t ulpClass:3;
3008 uint32_t ulpIr:1;
3009 uint32_t ulpPU:2;
3010 uint32_t ulpFCP2Rcvy:1;
3011 uint32_t ulpXS:1;
3012 uint32_t ulpTimeout:8;
3013#endif
3014 union {
3015 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
3016 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
3017 } unsli3;
2696
3018
3019#define ulpCt_h ulpXS
3020#define ulpCt_l ulpFCP2Rcvy
3021
3022#define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3023#define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
2697#define PARM_UNUSED 0 /* PU field (Word 4) not used */
2698#define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
2699#define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
2700#define CLASS1 0 /* Class 1 */
2701#define CLASS2 1 /* Class 2 */
2702#define CLASS3 2 /* Class 3 */
2703#define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
2704

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2719#define IOSTAT_RSVD4 0xE
2720#define IOSTAT_RSVD5 0xF
2721#define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
2722#define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
2723#define IOSTAT_CNT 0x11
2724
2725} IOCB_t;
2726
3024#define PARM_UNUSED 0 /* PU field (Word 4) not used */
3025#define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
3026#define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
3027#define CLASS1 0 /* Class 1 */
3028#define CLASS2 1 /* Class 2 */
3029#define CLASS3 2 /* Class 3 */
3030#define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
3031

--- 14 unchanged lines hidden (view full) ---

3046#define IOSTAT_RSVD4 0xE
3047#define IOSTAT_RSVD5 0xF
3048#define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
3049#define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
3050#define IOSTAT_CNT 0x11
3051
3052} IOCB_t;
3053
3054/* Structure used for a single HBQ entry */
3055struct lpfc_hbq_entry {
3056 struct ulp_bde64 bde;
3057 uint32_t buffer_tag;
3058};
2727
3059
3060
2728#define SLI1_SLIM_SIZE (4 * 1024)
2729
2730/* Up to 498 IOCBs will fit into 16k
2731 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
2732 */
3061#define SLI1_SLIM_SIZE (4 * 1024)
3062
3063/* Up to 498 IOCBs will fit into 16k
3064 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3065 */
2733#define SLI2_SLIM_SIZE (16 * 1024)
3066#define SLI2_SLIM_SIZE (64 * 1024)
2734
2735/* Maximum IOCBs that will fit in SLI2 slim */
2736#define MAX_SLI2_IOCB 498
3067
3068/* Maximum IOCBs that will fit in SLI2 slim */
3069#define MAX_SLI2_IOCB 498
3070#define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
3071 (sizeof(MAILBOX_t) + sizeof(PCB_t)))
2737
3072
3073/* HBQ entries are 4 words each = 4k */
3074#define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
3075 lpfc_sli_hbq_count())
3076
2738struct lpfc_sli2_slim {
2739 MAILBOX_t mbx;
2740 PCB_t pcb;
3077struct lpfc_sli2_slim {
3078 MAILBOX_t mbx;
3079 PCB_t pcb;
2741 IOCB_t IOCBs[MAX_SLI2_IOCB];
3080 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
2742};
2743
2744/*
2745 * This function checks PCI device to allow special handling for LC HBAs.
2746 *
2747 * Parameters:
2748 * device : struct pci_dev 's device field
2749 *

--- 18 unchanged lines hidden --- 		3081};
3082
3083/*
3084 * This function checks PCI device to allow special handling for LC HBAs.
3085 *
3086 * Parameters:
3087 * device : struct pci_dev 's device field
3088 *

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