pm-domains.c (a23e1966932464e1c5226cb9ac4ce1d5fc10ba22) pm-domains.c (cfee1b50775869de9076d021ea11a8438854dcba)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Rockchip Generic power domain support.
4 *
5 * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
6 */
7
8#include <linux/io.h>

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28#include <dt-bindings/power/rk3188-power.h>
29#include <dt-bindings/power/rk3228-power.h>
30#include <dt-bindings/power/rk3288-power.h>
31#include <dt-bindings/power/rk3328-power.h>
32#include <dt-bindings/power/rk3366-power.h>
33#include <dt-bindings/power/rk3368-power.h>
34#include <dt-bindings/power/rk3399-power.h>
35#include <dt-bindings/power/rk3568-power.h>
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Rockchip Generic power domain support.
4 *
5 * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
6 */
7
8#include <linux/io.h>

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28#include <dt-bindings/power/rk3188-power.h>
29#include <dt-bindings/power/rk3228-power.h>
30#include <dt-bindings/power/rk3288-power.h>
31#include <dt-bindings/power/rk3328-power.h>
32#include <dt-bindings/power/rk3366-power.h>
33#include <dt-bindings/power/rk3368-power.h>
34#include <dt-bindings/power/rk3399-power.h>
35#include <dt-bindings/power/rk3568-power.h>
36#include <dt-bindings/power/rockchip,rk3576-power.h>
36#include <dt-bindings/power/rk3588-power.h>
37
38struct rockchip_domain_info {
39 const char *name;
40 int pwr_mask;
41 int status_mask;
42 int req_mask;
43 int idle_mask;

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170 DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup)
171
172#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
173 DOMAIN(name, pwr, status, req, req, req, wakeup)
174
175#define DOMAIN_RK3568(name, pwr, req, wakeup) \
176 DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
177
37#include <dt-bindings/power/rk3588-power.h>
38
39struct rockchip_domain_info {
40 const char *name;
41 int pwr_mask;
42 int status_mask;
43 int req_mask;
44 int idle_mask;

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171 DOMAIN(name, pwr, status, req, (req) << 16, req, wakeup)
172
173#define DOMAIN_RK3399(name, pwr, status, req, wakeup) \
174 DOMAIN(name, pwr, status, req, req, req, wakeup)
175
176#define DOMAIN_RK3568(name, pwr, req, wakeup) \
177 DOMAIN_M(name, pwr, pwr, req, req, req, wakeup)
178
179#define DOMAIN_RK3576(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup) \
180 DOMAIN_M_O_R(name, p_offset, pwr, status, 0, r_status, r_status, r_offset, req, idle, idle, wakeup)
181
178/*
179 * Dynamic Memory Controller may need to coordinate with us -- see
180 * rockchip_pmu_block().
181 *
182 * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
183 * block() while we're initializing the PMU.
184 */
185static DEFINE_MUTEX(dmc_pmu_mutex);

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1101 [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false),
1102 [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false),
1103 [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false),
1104 [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false),
1105 [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false),
1106 [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
1107};
1108
182/*
183 * Dynamic Memory Controller may need to coordinate with us -- see
184 * rockchip_pmu_block().
185 *
186 * dmc_pmu_mutex protects registration-time races, so DMC driver doesn't try to
187 * block() while we're initializing the PMU.
188 */
189static DEFINE_MUTEX(dmc_pmu_mutex);

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1105 [RK3568_PD_VO] = DOMAIN_RK3568("vo", BIT(7), BIT(4), false),
1106 [RK3568_PD_RGA] = DOMAIN_RK3568("rga", BIT(5), BIT(5), false),
1107 [RK3568_PD_VPU] = DOMAIN_RK3568("vpu", BIT(2), BIT(6), false),
1108 [RK3568_PD_RKVDEC] = DOMAIN_RK3568("vdec", BIT(4), BIT(8), false),
1109 [RK3568_PD_RKVENC] = DOMAIN_RK3568("venc", BIT(3), BIT(7), false),
1110 [RK3568_PD_PIPE] = DOMAIN_RK3568("pipe", BIT(8), BIT(11), false),
1111};
1112
1113static const struct rockchip_domain_info rk3576_pm_domains[] = {
1114 [RK3576_PD_NPU] = DOMAIN_RK3576("npu", 0x0, BIT(0), BIT(0), 0, 0x0, 0, 0, false),
1115 [RK3576_PD_NVM] = DOMAIN_RK3576("nvm", 0x0, BIT(6), 0, BIT(6), 0x4, BIT(2), BIT(18), false),
1116 [RK3576_PD_SDGMAC] = DOMAIN_RK3576("sdgmac", 0x0, BIT(7), 0, BIT(7), 0x4, BIT(1), BIT(17), false),
1117 [RK3576_PD_AUDIO] = DOMAIN_RK3576("audio", 0x0, BIT(8), 0, BIT(8), 0x4, BIT(0), BIT(16), false),
1118 [RK3576_PD_PHP] = DOMAIN_RK3576("php", 0x0, BIT(9), 0, BIT(9), 0x0, BIT(15), BIT(15), false),
1119 [RK3576_PD_SUBPHP] = DOMAIN_RK3576("subphp", 0x0, BIT(10), 0, BIT(10), 0x0, 0, 0, false),
1120 [RK3576_PD_VOP] = DOMAIN_RK3576("vop", 0x0, BIT(11), 0, BIT(11), 0x0, 0x6000, 0x6000, false),
1121 [RK3576_PD_VO1] = DOMAIN_RK3576("vo1", 0x0, BIT(14), 0, BIT(14), 0x0, BIT(12), BIT(12), false),
1122 [RK3576_PD_VO0] = DOMAIN_RK3576("vo0", 0x0, BIT(15), 0, BIT(15), 0x0, BIT(11), BIT(11), false),
1123 [RK3576_PD_USB] = DOMAIN_RK3576("usb", 0x4, BIT(0), 0, BIT(16), 0x0, BIT(10), BIT(10), true),
1124 [RK3576_PD_VI] = DOMAIN_RK3576("vi", 0x4, BIT(1), 0, BIT(17), 0x0, BIT(9), BIT(9), false),
1125 [RK3576_PD_VEPU0] = DOMAIN_RK3576("vepu0", 0x4, BIT(2), 0, BIT(18), 0x0, BIT(7), BIT(7), false),
1126 [RK3576_PD_VEPU1] = DOMAIN_RK3576("vepu1", 0x4, BIT(3), 0, BIT(19), 0x0, BIT(8), BIT(8), false),
1127 [RK3576_PD_VDEC] = DOMAIN_RK3576("vdec", 0x4, BIT(4), 0, BIT(20), 0x0, BIT(6), BIT(6), false),
1128 [RK3576_PD_VPU] = DOMAIN_RK3576("vpu", 0x4, BIT(5), 0, BIT(21), 0x0, BIT(5), BIT(5), false),
1129 [RK3576_PD_NPUTOP] = DOMAIN_RK3576("nputop", 0x4, BIT(6), 0, BIT(22), 0x0, 0x18, 0x18, false),
1130 [RK3576_PD_NPU0] = DOMAIN_RK3576("npu0", 0x4, BIT(7), 0, BIT(23), 0x0, BIT(1), BIT(1), false),
1131 [RK3576_PD_NPU1] = DOMAIN_RK3576("npu1", 0x4, BIT(8), 0, BIT(24), 0x0, BIT(2), BIT(2), false),
1132 [RK3576_PD_GPU] = DOMAIN_RK3576("gpu", 0x4, BIT(9), 0, BIT(25), 0x0, BIT(0), BIT(0), false),
1133};
1134
1109static const struct rockchip_domain_info rk3588_pm_domains[] = {
1110 [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false),
1111 [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false),
1112 [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false),
1113 [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false),
1114 [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false),
1115 [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false),
1116 [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false),

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1279 .req_offset = 0x50,
1280 .idle_offset = 0x68,
1281 .ack_offset = 0x60,
1282
1283 .num_domains = ARRAY_SIZE(rk3568_pm_domains),
1284 .domain_info = rk3568_pm_domains,
1285};
1286
1135static const struct rockchip_domain_info rk3588_pm_domains[] = {
1136 [RK3588_PD_GPU] = DOMAIN_RK3588("gpu", 0x0, BIT(0), 0, 0x0, 0, BIT(1), 0x0, BIT(0), BIT(0), false),
1137 [RK3588_PD_NPU] = DOMAIN_RK3588("npu", 0x0, BIT(1), BIT(1), 0x0, 0, 0, 0x0, 0, 0, false),
1138 [RK3588_PD_VCODEC] = DOMAIN_RK3588("vcodec", 0x0, BIT(2), BIT(2), 0x0, 0, 0, 0x0, 0, 0, false),
1139 [RK3588_PD_NPUTOP] = DOMAIN_RK3588("nputop", 0x0, BIT(3), 0, 0x0, BIT(11), BIT(2), 0x0, BIT(1), BIT(1), false),
1140 [RK3588_PD_NPU1] = DOMAIN_RK3588("npu1", 0x0, BIT(4), 0, 0x0, BIT(12), BIT(3), 0x0, BIT(2), BIT(2), false),
1141 [RK3588_PD_NPU2] = DOMAIN_RK3588("npu2", 0x0, BIT(5), 0, 0x0, BIT(13), BIT(4), 0x0, BIT(3), BIT(3), false),
1142 [RK3588_PD_VENC0] = DOMAIN_RK3588("venc0", 0x0, BIT(6), 0, 0x0, BIT(14), BIT(5), 0x0, BIT(4), BIT(4), false),

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1305 .req_offset = 0x50,
1306 .idle_offset = 0x68,
1307 .ack_offset = 0x60,
1308
1309 .num_domains = ARRAY_SIZE(rk3568_pm_domains),
1310 .domain_info = rk3568_pm_domains,
1311};
1312
1313static const struct rockchip_pmu_info rk3576_pmu = {
1314 .pwr_offset = 0x210,
1315 .status_offset = 0x230,
1316 .chain_status_offset = 0x248,
1317 .mem_status_offset = 0x250,
1318 .mem_pwr_offset = 0x300,
1319 .req_offset = 0x110,
1320 .idle_offset = 0x128,
1321 .ack_offset = 0x120,
1322 .repair_status_offset = 0x570,
1323
1324 .num_domains = ARRAY_SIZE(rk3576_pm_domains),
1325 .domain_info = rk3576_pm_domains,
1326};
1327
1287static const struct rockchip_pmu_info rk3588_pmu = {
1288 .pwr_offset = 0x14c,
1289 .status_offset = 0x180,
1290 .req_offset = 0x10c,
1291 .idle_offset = 0x120,
1292 .ack_offset = 0x118,
1293 .mem_pwr_offset = 0x1a0,
1294 .chain_status_offset = 0x1f0,

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1355 .compatible = "rockchip,rk3399-power-controller",
1356 .data = (void *)&rk3399_pmu,
1357 },
1358 {
1359 .compatible = "rockchip,rk3568-power-controller",
1360 .data = (void *)&rk3568_pmu,
1361 },
1362 {
1328static const struct rockchip_pmu_info rk3588_pmu = {
1329 .pwr_offset = 0x14c,
1330 .status_offset = 0x180,
1331 .req_offset = 0x10c,
1332 .idle_offset = 0x120,
1333 .ack_offset = 0x118,
1334 .mem_pwr_offset = 0x1a0,
1335 .chain_status_offset = 0x1f0,

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1396 .compatible = "rockchip,rk3399-power-controller",
1397 .data = (void *)&rk3399_pmu,
1398 },
1399 {
1400 .compatible = "rockchip,rk3568-power-controller",
1401 .data = (void *)&rk3568_pmu,
1402 },
1403 {
1404 .compatible = "rockchip,rk3576-power-controller",
1405 .data = (void *)&rk3576_pmu,
1406 },
1407 {
1363 .compatible = "rockchip,rk3588-power-controller",
1364 .data = (void *)&rk3588_pmu,
1365 },
1366 {
1367 .compatible = "rockchip,rv1126-power-controller",
1368 .data = (void *)&rv1126_pmu,
1369 },
1370 { /* sentinel */ },

--- 21 unchanged lines hidden --- 		1408 .compatible = "rockchip,rk3588-power-controller",
1409 .data = (void *)&rk3588_pmu,
1410 },
1411 {
1412 .compatible = "rockchip,rv1126-power-controller",
1413 .data = (void *)&rv1126_pmu,
1414 },
1415 { /* sentinel */ },

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