pm-domains.c (4c621d6e667af6a41a0434fed6774abec7857801) pm-domains.c (8b579881de295d49a75f6312547f7813b1551a83)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Rockchip Generic power domain support.
4 *
5 * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
6 */
7
8#include <linux/io.h>

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41 int pwr_mask;
42 int status_mask;
43 int req_mask;
44 int idle_mask;
45 int ack_mask;
46 bool active_wakeup;
47 int pwr_w_mask;
48 int req_w_mask;
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Rockchip Generic power domain support.
4 *
5 * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
6 */
7
8#include <linux/io.h>

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41 int pwr_mask;
42 int status_mask;
43 int req_mask;
44 int idle_mask;
45 int ack_mask;
46 bool active_wakeup;
47 int pwr_w_mask;
48 int req_w_mask;
49 int clk_ungate_mask;
49 int mem_status_mask;
50 int repair_status_mask;
51 u32 pwr_offset;
52 u32 mem_offset;
53 u32 req_offset;
54};
55
56struct rockchip_pmu_info {
57 u32 pwr_offset;
58 u32 status_offset;
59 u32 req_offset;
60 u32 idle_offset;
61 u32 ack_offset;
62 u32 mem_pwr_offset;
63 u32 chain_status_offset;
64 u32 mem_status_offset;
65 u32 repair_status_offset;
50 int mem_status_mask;
51 int repair_status_mask;
52 u32 pwr_offset;
53 u32 mem_offset;
54 u32 req_offset;
55};
56
57struct rockchip_pmu_info {
58 u32 pwr_offset;
59 u32 status_offset;
60 u32 req_offset;
61 u32 idle_offset;
62 u32 ack_offset;
63 u32 mem_pwr_offset;
64 u32 chain_status_offset;
65 u32 mem_status_offset;
66 u32 repair_status_offset;
67 u32 clk_ungate_offset;
66
67 u32 core_pwrcnt_offset;
68 u32 gpu_pwrcnt_offset;
69
70 unsigned int core_power_transition_time;
71 unsigned int gpu_power_transition_time;
72
73 int num_domains;

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298static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
299{
300 unsigned int val;
301
302 regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
303 return val;
304}
305
68
69 u32 core_pwrcnt_offset;
70 u32 gpu_pwrcnt_offset;
71
72 unsigned int core_power_transition_time;
73 unsigned int gpu_power_transition_time;
74
75 int num_domains;

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300static unsigned int rockchip_pmu_read_ack(struct rockchip_pmu *pmu)
301{
302 unsigned int val;
303
304 regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
305 return val;
306}
307
308static int rockchip_pmu_ungate_clk(struct rockchip_pm_domain *pd, bool ungate)
309{
310 const struct rockchip_domain_info *pd_info = pd->info;
311 struct rockchip_pmu *pmu = pd->pmu;
312 unsigned int val;
313 int clk_ungate_w_mask = pd_info->clk_ungate_mask << 16;
314
315 if (!pd_info->clk_ungate_mask)
316 return 0;
317
318 if (!pmu->info->clk_ungate_offset)
319 return 0;
320
321 val = ungate ? (pd_info->clk_ungate_mask | clk_ungate_w_mask) :
322 clk_ungate_w_mask;
323 regmap_write(pmu->regmap, pmu->info->clk_ungate_offset, val);
324
325 return 0;
326}
327
306static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
307 bool idle)
308{
309 const struct rockchip_domain_info *pd_info = pd->info;
310 struct generic_pm_domain *genpd = &pd->genpd;
311 struct rockchip_pmu *pmu = pd->pmu;
312 u32 pd_req_offset = pd_info->req_offset;
313 unsigned int target_ack;

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538 if (rockchip_pmu_domain_is_on(pd) != power_on) {
539 ret = clk_bulk_enable(pd->num_clks, pd->clks);
540 if (ret < 0) {
541 dev_err(pmu->dev, "failed to enable clocks\n");
542 mutex_unlock(&pmu->mutex);
543 return ret;
544 }
545
328static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
329 bool idle)
330{
331 const struct rockchip_domain_info *pd_info = pd->info;
332 struct generic_pm_domain *genpd = &pd->genpd;
333 struct rockchip_pmu *pmu = pd->pmu;
334 u32 pd_req_offset = pd_info->req_offset;
335 unsigned int target_ack;

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560 if (rockchip_pmu_domain_is_on(pd) != power_on) {
561 ret = clk_bulk_enable(pd->num_clks, pd->clks);
562 if (ret < 0) {
563 dev_err(pmu->dev, "failed to enable clocks\n");
564 mutex_unlock(&pmu->mutex);
565 return ret;
566 }
567
568 rockchip_pmu_ungate_clk(pd, true);
569
546 if (!power_on) {
547 rockchip_pmu_save_qos(pd);
548
549 /* if powering down, idle request to NIU first */
550 rockchip_pmu_set_idle_request(pd, true);
551 }
552
553 rockchip_do_pmu_set_power_domain(pd, power_on);
554
555 if (power_on) {
556 /* if powering up, leave idle mode */
557 rockchip_pmu_set_idle_request(pd, false);
558
559 rockchip_pmu_restore_qos(pd);
560 }
561
570 if (!power_on) {
571 rockchip_pmu_save_qos(pd);
572
573 /* if powering down, idle request to NIU first */
574 rockchip_pmu_set_idle_request(pd, true);
575 }
576
577 rockchip_do_pmu_set_power_domain(pd, power_on);
578
579 if (power_on) {
580 /* if powering up, leave idle mode */
581 rockchip_pmu_set_idle_request(pd, false);
582
583 rockchip_pmu_restore_qos(pd);
584 }
585
586 rockchip_pmu_ungate_clk(pd, false);
562 clk_bulk_disable(pd->num_clks, pd->clks);
563 }
564
565 mutex_unlock(&pmu->mutex);
566 return 0;
567}
568
569static int rockchip_pd_power_on(struct generic_pm_domain *domain)

--- 855 unchanged lines hidden --- 		587 clk_bulk_disable(pd->num_clks, pd->clks);
588 }
589
590 mutex_unlock(&pmu->mutex);
591 return 0;
592}
593
594static int rockchip_pd_power_on(struct generic_pm_domain *domain)

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