pmf.h (2b3a7f06caaf1aa7379cc0233462799852fcd8b4) pmf.h (7c45534afa4435c9fceeeb8ca33c0fdc269c2240)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * AMD Platform Management Framework Driver
4 *
5 * Copyright (c) 2022, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9 */
10
11#ifndef PMF_H
12#define PMF_H
13
14#include <linux/acpi.h>
15#include <linux/platform_profile.h>
16
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * AMD Platform Management Framework Driver
4 *
5 * Copyright (c) 2022, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9 */
10
11#ifndef PMF_H
12#define PMF_H
13
14#include <linux/acpi.h>
15#include <linux/platform_profile.h>
16
17#define POLICY_BUF_MAX_SZ 0x4b000
18#define POLICY_SIGN_COOKIE 0x31535024
19#define POLICY_COOKIE_OFFSET 0x10
20#define POLICY_COOKIE_LEN 0x14
21
17/* APMF Functions */
18#define APMF_FUNC_VERIFY_INTERFACE 0
19#define APMF_FUNC_GET_SYS_PARAMS 1
20#define APMF_FUNC_SBIOS_REQUESTS 2
21#define APMF_FUNC_SBIOS_HEARTBEAT 4
22#define APMF_FUNC_AUTO_MODE 5
23#define APMF_FUNC_SET_FAN_IDX 7
24#define APMF_FUNC_OS_POWER_SLIDER_UPDATE 8

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54#define AC_BETTER_BATTERY 6
55
56/* Fan Index for Auto Mode */
57#define FAN_INDEX_AUTO 0xFFFFFFFF
58
59#define ARG_NONE 0
60#define AVG_SAMPLE_SIZE 3
61
22/* APMF Functions */
23#define APMF_FUNC_VERIFY_INTERFACE 0
24#define APMF_FUNC_GET_SYS_PARAMS 1
25#define APMF_FUNC_SBIOS_REQUESTS 2
26#define APMF_FUNC_SBIOS_HEARTBEAT 4
27#define APMF_FUNC_AUTO_MODE 5
28#define APMF_FUNC_SET_FAN_IDX 7
29#define APMF_FUNC_OS_POWER_SLIDER_UPDATE 8

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59#define AC_BETTER_BATTERY 6
60
61/* Fan Index for Auto Mode */
62#define FAN_INDEX_AUTO 0xFFFFFFFF
63
64#define ARG_NONE 0
65#define AVG_SAMPLE_SIZE 3
66
67/* Policy Actions */
68#define PMF_POLICY_SPL 2
69#define PMF_POLICY_SPPT 3
70#define PMF_POLICY_FPPT 4
71#define PMF_POLICY_SPPT_APU_ONLY 5
72#define PMF_POLICY_STT_MIN 6
73#define PMF_POLICY_STT_SKINTEMP_APU 7
74#define PMF_POLICY_STT_SKINTEMP_HS2 8
75
62/* TA macros */
63#define PMF_TA_IF_VERSION_MAJOR 1
76/* TA macros */
77#define PMF_TA_IF_VERSION_MAJOR 1
78#define TA_PMF_ACTION_MAX 32
79#define TA_PMF_UNDO_MAX 8
80#define TA_OUTPUT_RESERVED_MEM 906
81#define MAX_OPERATION_PARAMS 4
64
65/* AMD PMF BIOS interfaces */
66struct apmf_verify_interface {
67 u16 size;
68 u16 version;
69 u32 notification_mask;
70 u32 supported_functions;
71} __packed;

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178 int socket_power_history[AVG_SAMPLE_SIZE];
179 int socket_power_history_idx;
180 bool amt_enabled;
181 struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */
182 bool cnqf_enabled;
183 bool cnqf_supported;
184 struct notifier_block pwr_src_notifier;
185 /* Smart PC solution builder */
82
83/* AMD PMF BIOS interfaces */
84struct apmf_verify_interface {
85 u16 size;
86 u16 version;
87 u32 notification_mask;
88 u32 supported_functions;
89} __packed;

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196 int socket_power_history[AVG_SAMPLE_SIZE];
197 int socket_power_history_idx;
198 bool amt_enabled;
199 struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */
200 bool cnqf_enabled;
201 bool cnqf_supported;
202 struct notifier_block pwr_src_notifier;
203 /* Smart PC solution builder */
204 unsigned char *policy_buf;
205 u32 policy_sz;
186 struct tee_context *tee_ctx;
187 struct tee_shm *fw_shm_pool;
188 u32 session_id;
189 void *shbuf;
190 struct delayed_work pb_work;
206 struct tee_context *tee_ctx;
207 struct tee_shm *fw_shm_pool;
208 u32 session_id;
209 void *shbuf;
210 struct delayed_work pb_work;
211 struct pmf_action_table *prev_data;
212 u64 policy_addr;
213 void *policy_base;
191 bool smart_pc_enabled;
192};
193
194struct apmf_sps_prop_granular {
195 u32 fppt;
196 u32 sppt;
197 u32 sppt_apu_only;
198 u32 spl;

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394 u32 t_balanced_to_perf;
395 u32 t_quiet_to_balanced;
396 u32 t_balanced_to_quiet;
397 u32 t_perf_to_balanced;
398 u32 t_turbo_to_perf;
399 struct apmf_cnqf_power_set ps[APMF_CNQF_MAX];
400} __packed;
401
214 bool smart_pc_enabled;
215};
216
217struct apmf_sps_prop_granular {
218 u32 fppt;
219 u32 sppt;
220 u32 sppt_apu_only;
221 u32 spl;

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417 u32 t_balanced_to_perf;
418 u32 t_quiet_to_balanced;
419 u32 t_balanced_to_quiet;
420 u32 t_perf_to_balanced;
421 u32 t_turbo_to_perf;
422 struct apmf_cnqf_power_set ps[APMF_CNQF_MAX];
423} __packed;
424
425enum smart_pc_status {
426 PMF_SMART_PC_ENABLED,
427 PMF_SMART_PC_DISABLED,
428};
429
430/* Smart PC - TA internals */
431enum ta_slider {
432 TA_BEST_BATTERY,
433 TA_BETTER_BATTERY,
434 TA_BETTER_PERFORMANCE,
435 TA_BEST_PERFORMANCE,
436 TA_MAX,
437};
438
402/* Command ids for TA communication */
403enum ta_pmf_command {
404 TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE,
405 TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES,
406};
407
439/* Command ids for TA communication */
440enum ta_pmf_command {
441 TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE,
442 TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES,
443};
444
445enum ta_pmf_error_type {
446 TA_PMF_TYPE_SUCCESS,
447 TA_PMF_ERROR_TYPE_GENERIC,
448 TA_PMF_ERROR_TYPE_CRYPTO,
449 TA_PMF_ERROR_TYPE_CRYPTO_VALIDATE,
450 TA_PMF_ERROR_TYPE_CRYPTO_VERIFY_OEM,
451 TA_PMF_ERROR_TYPE_POLICY_BUILDER,
452 TA_PMF_ERROR_TYPE_PB_CONVERT,
453 TA_PMF_ERROR_TYPE_PB_SETUP,
454 TA_PMF_ERROR_TYPE_PB_ENACT,
455 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_INFO,
456 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_PCIE_INFO,
457 TA_PMF_ERROR_TYPE_SYS_DRV_FW_VALIDATION,
458 TA_PMF_ERROR_TYPE_MAX,
459};
460
461struct pmf_action_table {
462 u32 spl; /* in mW */
463 u32 sppt; /* in mW */
464 u32 sppt_apuonly; /* in mW */
465 u32 fppt; /* in mW */
466 u32 stt_minlimit; /* in mW */
467 u32 stt_skintemp_apu; /* in C */
468 u32 stt_skintemp_hs2; /* in C */
469};
470
471/* Input conditions */
472struct ta_pmf_condition_info {
473 u32 power_source;
474 u32 bat_percentage;
475 u32 power_slider;
476 u32 lid_state;
477 bool user_present;
478 u32 rsvd1[2];
479 u32 monitor_count;
480 u32 rsvd2[2];
481 u32 bat_design;
482 u32 full_charge_capacity;
483 int drain_rate;
484 bool user_engaged;
485 u32 device_state;
486 u32 socket_power;
487 u32 skin_temperature;
488 u32 rsvd3[5];
489 u32 ambient_light;
490 u32 length;
491 u32 avg_c0residency;
492 u32 max_c0residency;
493 u32 s0i3_entry;
494 u32 gfx_busy;
495 u32 rsvd4[7];
496 bool camera_state;
497 u32 workload_type;
498 u32 display_type;
499 u32 display_state;
500 u32 rsvd5[150];
501};
502
503struct ta_pmf_load_policy_table {
504 u32 table_size;
505 u8 table[POLICY_BUF_MAX_SZ];
506};
507
508/* TA initialization params */
509struct ta_pmf_init_table {
510 u32 frequency; /* SMU sampling frequency */
511 bool validate;
512 bool sku_check;
513 bool metadata_macrocheck;
514 struct ta_pmf_load_policy_table policies_table;
515};
516
517/* Everything the TA needs to Enact Policies */
518struct ta_pmf_enact_table {
519 struct ta_pmf_condition_info ev_info;
520 u32 name;
521};
522
523struct ta_pmf_action {
524 u32 action_index;
525 u32 value;
526};
527
528/* Output actions from TA */
529struct ta_pmf_enact_result {
530 u32 actions_count;
531 struct ta_pmf_action actions_list[TA_PMF_ACTION_MAX];
532 u32 undo_count;
533 struct ta_pmf_action undo_list[TA_PMF_UNDO_MAX];
534};
535
536union ta_pmf_input {
537 struct ta_pmf_enact_table enact_table;
538 struct ta_pmf_init_table init_table;
539};
540
541union ta_pmf_output {
542 struct ta_pmf_enact_result policy_apply_table;
543 u32 rsvd[TA_OUTPUT_RESERVED_MEM];
544};
545
408struct ta_pmf_shared_memory {
409 int command_id;
410 int resp_id;
411 u32 pmf_result;
412 u32 if_version;
546struct ta_pmf_shared_memory {
547 int command_id;
548 int resp_id;
549 u32 pmf_result;
550 u32 if_version;
551 union ta_pmf_output pmf_output;
552 union ta_pmf_input pmf_input;
413};
414
415/* Core Layer */
416int apmf_acpi_init(struct amd_pmf_dev *pmf_dev);
417void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev);
418int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index);
419int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data);
420int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev);

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455int amd_pmf_init_cnqf(struct amd_pmf_dev *dev);
456void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev);
457int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms);
458extern const struct attribute_group cnqf_feature_attribute_group;
459
460/* Smart PC builder Layer */
461int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev);
462void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev);
553};
554
555/* Core Layer */
556int apmf_acpi_init(struct amd_pmf_dev *pmf_dev);
557void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev);
558int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index);
559int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data);
560int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev);

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595int amd_pmf_init_cnqf(struct amd_pmf_dev *dev);
596void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev);
597int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms);
598extern const struct attribute_group cnqf_feature_attribute_group;
599
600/* Smart PC builder Layer */
601int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev);
602void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev);
603int apmf_check_smart_pc(struct amd_pmf_dev *pmf_dev);
463#endif /* PMF_H */
604#endif /* PMF_H */