pinctrl-ocelot.c (a3479c7fc096a1a7a2dccbfbdc6fcf86b805711a) pinctrl-ocelot.c (be36abb71d878f3320412a84e6bbec8dd796010c)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi SoCs pinctrl driver
4 *
5 * Author: <alexandre.belloni@free-electrons.com>
6 * License: Dual MIT/GPL
7 * Copyright (c) 2017 Microsemi Corporation
8 */
9
10#include <linux/gpio/driver.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/of_device.h>
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi SoCs pinctrl driver
4 *
5 * Author: <alexandre.belloni@free-electrons.com>
6 * License: Dual MIT/GPL
7 * Copyright (c) 2017 Microsemi Corporation
8 */
9
10#include <linux/gpio/driver.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/of_device.h>
14#include <linux/of_irq.h>
14#include <linux/of_platform.h>
15#include <linux/pinctrl/pinctrl.h>
16#include <linux/pinctrl/pinmux.h>
17#include <linux/pinctrl/pinconf.h>
18#include <linux/pinctrl/pinconf-generic.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21#include <linux/slab.h>

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127 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
128 }, \
129}
130
131OCELOT_P(0, SG0, NONE, NONE);
132OCELOT_P(1, SG0, NONE, NONE);
133OCELOT_P(2, SG0, NONE, NONE);
134OCELOT_P(3, SG0, NONE, NONE);
15#include <linux/of_platform.h>
16#include <linux/pinctrl/pinctrl.h>
17#include <linux/pinctrl/pinmux.h>
18#include <linux/pinctrl/pinconf.h>
19#include <linux/pinctrl/pinconf-generic.h>
20#include <linux/platform_device.h>
21#include <linux/regmap.h>
22#include <linux/slab.h>

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128 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
129 }, \
130}
131
132OCELOT_P(0, SG0, NONE, NONE);
133OCELOT_P(1, SG0, NONE, NONE);
134OCELOT_P(2, SG0, NONE, NONE);
135OCELOT_P(3, SG0, NONE, NONE);
135OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI);
136OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
136OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
137OCELOT_P(6, UART, TWI_SCL_M, NONE);
138OCELOT_P(7, UART, TWI_SCL_M, NONE);
139OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
140OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
141OCELOT_P(10, PTP2, TWI_SCL_M, SFP0);
142OCELOT_P(11, PTP3, TWI_SCL_M, SFP1);
143OCELOT_P(12, UART2, TWI_SCL_M, SFP2);

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422 .set = ocelot_gpio_set,
423 .get = ocelot_gpio_get,
424 .get_direction = ocelot_gpio_get_direction,
425 .direction_input = ocelot_gpio_direction_input,
426 .direction_output = ocelot_gpio_direction_output,
427 .owner = THIS_MODULE,
428};
429
137OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
138OCELOT_P(6, UART, TWI_SCL_M, NONE);
139OCELOT_P(7, UART, TWI_SCL_M, NONE);
140OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
141OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
142OCELOT_P(10, PTP2, TWI_SCL_M, SFP0);
143OCELOT_P(11, PTP3, TWI_SCL_M, SFP1);
144OCELOT_P(12, UART2, TWI_SCL_M, SFP2);

--- 278 unchanged lines hidden (view full) ---

423 .set = ocelot_gpio_set,
424 .get = ocelot_gpio_get,
425 .get_direction = ocelot_gpio_get_direction,
426 .direction_input = ocelot_gpio_direction_input,
427 .direction_output = ocelot_gpio_direction_output,
428 .owner = THIS_MODULE,
429};
430
431static void ocelot_irq_mask(struct irq_data *data)
432{
433 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
434 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
435 unsigned int gpio = irqd_to_hwirq(data);
436
437 regmap_update_bits(info->map, OCELOT_GPIO_INTR_ENA, BIT(gpio), 0);
438}
439
440static void ocelot_irq_unmask(struct irq_data *data)
441{
442 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
443 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
444 unsigned int gpio = irqd_to_hwirq(data);
445
446 regmap_update_bits(info->map, OCELOT_GPIO_INTR_ENA, BIT(gpio),
447 BIT(gpio));
448}
449
450static void ocelot_irq_ack(struct irq_data *data)
451{
452 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
453 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
454 unsigned int gpio = irqd_to_hwirq(data);
455
456 regmap_write_bits(info->map, OCELOT_GPIO_INTR, BIT(gpio), BIT(gpio));
457}
458
459static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
460
461static struct irq_chip ocelot_eoi_irqchip = {
462 .name = "gpio",
463 .irq_mask = ocelot_irq_mask,
464 .irq_eoi = ocelot_irq_ack,
465 .irq_unmask = ocelot_irq_unmask,
466 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED,
467 .irq_set_type = ocelot_irq_set_type,
468};
469
470static struct irq_chip ocelot_irqchip = {
471 .name = "gpio",
472 .irq_mask = ocelot_irq_mask,
473 .irq_ack = ocelot_irq_ack,
474 .irq_unmask = ocelot_irq_unmask,
475 .irq_set_type = ocelot_irq_set_type,
476};
477
478static int ocelot_irq_set_type(struct irq_data *data, unsigned int type)
479{
480 type &= IRQ_TYPE_SENSE_MASK;
481
482 if (!(type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_HIGH)))
483 return -EINVAL;
484
485 if (type & IRQ_TYPE_LEVEL_HIGH)
486 irq_set_chip_handler_name_locked(data, &ocelot_eoi_irqchip,
487 handle_fasteoi_irq, NULL);
488 if (type & IRQ_TYPE_EDGE_BOTH)
489 irq_set_chip_handler_name_locked(data, &ocelot_irqchip,
490 handle_edge_irq, NULL);
491
492 return 0;
493}
494
495static void ocelot_irq_handler(struct irq_desc *desc)
496{
497 struct irq_chip *parent_chip = irq_desc_get_chip(desc);
498 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
499 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
500 unsigned int reg = 0, irq;
501 unsigned long irqs;
502
503 regmap_read(info->map, OCELOT_GPIO_INTR_IDENT, &reg);
504 if (!reg)
505 return;
506
507 chained_irq_enter(parent_chip, desc);
508
509 irqs = reg;
510
511 for_each_set_bit(irq, &irqs, OCELOT_PINS) {
512 generic_handle_irq(irq_linear_revmap(chip->irq.domain, irq));
513 }
514
515 chained_irq_exit(parent_chip, desc);
516}
517
430static int ocelot_gpiochip_register(struct platform_device *pdev,
431 struct ocelot_pinctrl *info)
432{
433 struct gpio_chip *gc;
518static int ocelot_gpiochip_register(struct platform_device *pdev,
519 struct ocelot_pinctrl *info)
520{
521 struct gpio_chip *gc;
434 int ret;
522 int ret, irq;
435
436 info->gpio_chip = ocelot_gpiolib_chip;
437
438 gc = &info->gpio_chip;
439 gc->ngpio = OCELOT_PINS;
440 gc->parent = &pdev->dev;
441 gc->base = 0;
442 gc->of_node = info->dev->of_node;
443 gc->label = "ocelot-gpio";
444
445 ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
446 if (ret)
447 return ret;
448
523
524 info->gpio_chip = ocelot_gpiolib_chip;
525
526 gc = &info->gpio_chip;
527 gc->ngpio = OCELOT_PINS;
528 gc->parent = &pdev->dev;
529 gc->base = 0;
530 gc->of_node = info->dev->of_node;
531 gc->label = "ocelot-gpio";
532
533 ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
534 if (ret)
535 return ret;
536
449 /* TODO: this can be used as an irqchip but no board is using that */
537 irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
538 if (irq <= 0)
539 return irq;
450
540
541 ret = gpiochip_irqchip_add(gc, &ocelot_irqchip, 0, handle_edge_irq,
542 IRQ_TYPE_NONE);
543 if (ret)
544 return ret;
545
546 gpiochip_set_chained_irqchip(gc, &ocelot_irqchip, irq,
547 ocelot_irq_handler);
548
451 return 0;
452}
453
454static const struct regmap_config ocelot_pinctrl_regmap_config = {
455 .reg_bits = 32,
456 .val_bits = 32,
457 .reg_stride = 4,
458 .max_register = 0x64,

--- 54 unchanged lines hidden --- 		549 return 0;
550}
551
552static const struct regmap_config ocelot_pinctrl_regmap_config = {
553 .reg_bits = 32,
554 .val_bits = 32,
555 .reg_stride = 4,
556 .max_register = 0x64,

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