pinctrl-microchip-sgpio.c (d05b7691904b4b754b8469aa98a6b82523fdadad) pinctrl-microchip-sgpio.c (be2dc859abd4d7ad5e0f5d12ed767a3313b4e839)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Microsemi/Microchip SoCs serial gpio driver
4 *
5 * Author: Lars Povlsen <lars.povlsen@microchip.com>
6 *
7 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
8 */

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26#define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */
27
28enum {
29 REG_INPUT_DATA,
30 REG_PORT_CONFIG,
31 REG_PORT_ENABLE,
32 REG_SIO_CONFIG,
33 REG_SIO_CLOCK,
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Microsemi/Microchip SoCs serial gpio driver
4 *
5 * Author: Lars Povlsen <lars.povlsen@microchip.com>
6 *
7 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
8 */

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26#define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */
27
28enum {
29 REG_INPUT_DATA,
30 REG_PORT_CONFIG,
31 REG_PORT_ENABLE,
32 REG_SIO_CONFIG,
33 REG_SIO_CLOCK,
34 REG_INT_POLARITY,
35 REG_INT_TRIGGER,
36 REG_INT_ACK,
37 REG_INT_ENABLE,
38 REG_INT_IDENT,
34 MAXREG
35};
36
37enum {
38 SGPIO_ARCH_LUTON,
39 SGPIO_ARCH_OCELOT,
40 SGPIO_ARCH_SPARX5,
41};
42
39 MAXREG
40};
41
42enum {
43 SGPIO_ARCH_LUTON,
44 SGPIO_ARCH_OCELOT,
45 SGPIO_ARCH_SPARX5,
46};
47
48enum {
49 SGPIO_FLAGS_HAS_IRQ = BIT(0),
50};
51
43struct sgpio_properties {
44 int arch;
52struct sgpio_properties {
53 int arch;
54 int flags;
45 u8 regoff[MAXREG];
46};
47
48#define SGPIO_LUTON_AUTO_REPEAT BIT(5)
49#define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2)
50#define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0)
51#define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0)
52
53#define SGPIO_OCELOT_AUTO_REPEAT BIT(10)
54#define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7)
55#define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8)
56#define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12)
57
58#define SGPIO_SPARX5_AUTO_REPEAT BIT(6)
59#define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3)
60#define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8)
61#define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12)
62
55 u8 regoff[MAXREG];
56};
57
58#define SGPIO_LUTON_AUTO_REPEAT BIT(5)
59#define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2)
60#define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0)
61#define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0)
62
63#define SGPIO_OCELOT_AUTO_REPEAT BIT(10)
64#define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7)
65#define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8)
66#define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12)
67
68#define SGPIO_SPARX5_AUTO_REPEAT BIT(6)
69#define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3)
70#define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8)
71#define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12)
72
73#define SGPIO_MASTER_INTR_ENA BIT(0)
74
75#define SGPIO_INT_TRG_LEVEL 0
76#define SGPIO_INT_TRG_EDGE 1
77#define SGPIO_INT_TRG_EDGE_FALL 2
78#define SGPIO_INT_TRG_EDGE_RISE 3
79
80#define SGPIO_TRG_LEVEL_HIGH 0
81#define SGPIO_TRG_LEVEL_LOW 1
82
63static const struct sgpio_properties properties_luton = {
64 .arch = SGPIO_ARCH_LUTON,
65 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
66};
67
68static const struct sgpio_properties properties_ocelot = {
69 .arch = SGPIO_ARCH_OCELOT,
70 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
71};
72
73static const struct sgpio_properties properties_sparx5 = {
74 .arch = SGPIO_ARCH_SPARX5,
83static const struct sgpio_properties properties_luton = {
84 .arch = SGPIO_ARCH_LUTON,
85 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b },
86};
87
88static const struct sgpio_properties properties_ocelot = {
89 .arch = SGPIO_ARCH_OCELOT,
90 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
91};
92
93static const struct sgpio_properties properties_sparx5 = {
94 .arch = SGPIO_ARCH_SPARX5,
75 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 },
95 .flags = SGPIO_FLAGS_HAS_IRQ,
96 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 },
76};
77
78static const char * const functions[] = { "gpio" };
79
80struct sgpio_bank {
81 struct sgpio_priv *priv;
82 bool is_input;
83 struct gpio_chip gpio;

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102
103static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin,
104 struct sgpio_port_addr *addr)
105{
106 addr->port = pin / priv->bitcount;
107 addr->bit = pin % priv->bitcount;
108}
109
97};
98
99static const char * const functions[] = { "gpio" };
100
101struct sgpio_bank {
102 struct sgpio_priv *priv;
103 bool is_input;
104 struct gpio_chip gpio;

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123
124static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin,
125 struct sgpio_port_addr *addr)
126{
127 addr->port = pin / priv->bitcount;
128 addr->bit = pin % priv->bitcount;
129}
130
131static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit)
132{
133 return bit + port * priv->bitcount;
134}
135
110static inline u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off)
111{
112 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off];
113
114 return readl(reg);
115}
116
117static inline void sgpio_writel(struct sgpio_priv *priv,

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473 /*
474 * Note that the SGIO pin is defined by *2* numbers, a port
475 * number between 0 and 31, and a bit index, 0 to 3.
476 */
477 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD ||
478 gpiospec->args[1] > priv->bitcount)
479 return -EINVAL;
480
136static inline u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off)
137{
138 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off];
139
140 return readl(reg);
141}
142
143static inline void sgpio_writel(struct sgpio_priv *priv,

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499 /*
500 * Note that the SGIO pin is defined by *2* numbers, a port
501 * number between 0 and 31, and a bit index, 0 to 3.
502 */
503 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD ||
504 gpiospec->args[1] > priv->bitcount)
505 return -EINVAL;
506
481 pin = gpiospec->args[1] + gpiospec->args[0] * priv->bitcount;
507 pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]);
482
483 if (pin > gc->ngpio)
484 return -EINVAL;
485
486 if (flags)
487 *flags = gpiospec->args[2];
488
489 return pin;

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522 start, end);
523 }
524 priv->ports |= GENMASK(end, start);
525 }
526
527 return 0;
528}
529
508
509 if (pin > gc->ngpio)
510 return -EINVAL;
511
512 if (flags)
513 *flags = gpiospec->args[2];
514
515 return pin;

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548 start, end);
549 }
550 priv->ports |= GENMASK(end, start);
551 }
552
553 return 0;
554}
555
556static void microchip_sgpio_irq_settype(struct irq_data *data,
557 int type,
558 int polarity)
559{
560 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
561 struct sgpio_bank *bank = gpiochip_get_data(chip);
562 unsigned int gpio = irqd_to_hwirq(data);
563 struct sgpio_port_addr addr;
564 u32 ena;
565
566 sgpio_pin_to_addr(bank->priv, gpio, &addr);
567
568 /* Disable interrupt while changing type */
569 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit);
570 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit);
571
572 /* Type value spread over 2 registers sets: low, high bit */
573 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit,
574 BIT(addr.port), (!!(type & 0x1)) << addr.port);
575 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER + SGPIO_MAX_BITS, addr.bit,
576 BIT(addr.port), (!!(type & 0x2)) << addr.port);
577
578 if (type == SGPIO_INT_TRG_LEVEL)
579 sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit,
580 BIT(addr.port), polarity << addr.port);
581
582 /* Possibly re-enable interrupts */
583 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit);
584}
585
586static void microchip_sgpio_irq_setreg(struct irq_data *data,
587 int reg,
588 bool clear)
589{
590 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
591 struct sgpio_bank *bank = gpiochip_get_data(chip);
592 unsigned int gpio = irqd_to_hwirq(data);
593 struct sgpio_port_addr addr;
594
595 sgpio_pin_to_addr(bank->priv, gpio, &addr);
596
597 if (clear)
598 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0);
599 else
600 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port));
601}
602
603static void microchip_sgpio_irq_mask(struct irq_data *data)
604{
605 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true);
606}
607
608static void microchip_sgpio_irq_unmask(struct irq_data *data)
609{
610 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false);
611}
612
613static void microchip_sgpio_irq_ack(struct irq_data *data)
614{
615 microchip_sgpio_irq_setreg(data, REG_INT_ACK, false);
616}
617
618static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type)
619{
620 type &= IRQ_TYPE_SENSE_MASK;
621
622 switch (type) {
623 case IRQ_TYPE_EDGE_BOTH:
624 irq_set_handler_locked(data, handle_edge_irq);
625 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0);
626 break;
627 case IRQ_TYPE_EDGE_RISING:
628 irq_set_handler_locked(data, handle_edge_irq);
629 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0);
630 break;
631 case IRQ_TYPE_EDGE_FALLING:
632 irq_set_handler_locked(data, handle_edge_irq);
633 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0);
634 break;
635 case IRQ_TYPE_LEVEL_HIGH:
636 irq_set_handler_locked(data, handle_level_irq);
637 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH);
638 break;
639 case IRQ_TYPE_LEVEL_LOW:
640 irq_set_handler_locked(data, handle_level_irq);
641 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW);
642 break;
643 default:
644 return -EINVAL;
645 }
646
647 return 0;
648}
649
650static const struct irq_chip microchip_sgpio_irqchip = {
651 .name = "gpio",
652 .irq_mask = microchip_sgpio_irq_mask,
653 .irq_ack = microchip_sgpio_irq_ack,
654 .irq_unmask = microchip_sgpio_irq_unmask,
655 .irq_set_type = microchip_sgpio_irq_set_type,
656};
657
658static void sgpio_irq_handler(struct irq_desc *desc)
659{
660 struct irq_chip *parent_chip = irq_desc_get_chip(desc);
661 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
662 struct sgpio_bank *bank = gpiochip_get_data(chip);
663 struct sgpio_priv *priv = bank->priv;
664 int bit, port, gpio;
665 long val;
666
667 for (bit = 0; bit < priv->bitcount; bit++) {
668 val = sgpio_readl(priv, REG_INT_IDENT, bit);
669 if (!val)
670 continue;
671
672 chained_irq_enter(parent_chip, desc);
673
674 for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) {
675 gpio = sgpio_addr_to_pin(priv, port, bit);
676 generic_handle_irq(irq_linear_revmap(chip->irq.domain, gpio));
677 }
678
679 chained_irq_exit(parent_chip, desc);
680 }
681}
682
530static int microchip_sgpio_register_bank(struct device *dev,
531 struct sgpio_priv *priv,
532 struct fwnode_handle *fwnode,
533 int bankno)
534{
535 struct pinctrl_pin_desc *pins;
536 struct pinctrl_desc *pctl_desc;
537 struct pinctrl_dev *pctldev;

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603 gc->set = microchip_sgpio_set_value;
604 gc->request = gpiochip_generic_request;
605 gc->free = gpiochip_generic_free;
606 gc->of_xlate = microchip_sgpio_of_xlate;
607 gc->of_gpio_n_cells = 3;
608 gc->base = -1;
609 gc->ngpio = ngpios;
610
683static int microchip_sgpio_register_bank(struct device *dev,
684 struct sgpio_priv *priv,
685 struct fwnode_handle *fwnode,
686 int bankno)
687{
688 struct pinctrl_pin_desc *pins;
689 struct pinctrl_desc *pctl_desc;
690 struct pinctrl_dev *pctldev;

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756 gc->set = microchip_sgpio_set_value;
757 gc->request = gpiochip_generic_request;
758 gc->free = gpiochip_generic_free;
759 gc->of_xlate = microchip_sgpio_of_xlate;
760 gc->of_gpio_n_cells = 3;
761 gc->base = -1;
762 gc->ngpio = ngpios;
763
764 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) {
765 int irq = fwnode_irq_get(fwnode, 0);
766
767 if (irq) {
768 struct gpio_irq_chip *girq = &gc->irq;
769
770 girq->chip = devm_kmemdup(dev, &microchip_sgpio_irqchip,
771 sizeof(microchip_sgpio_irqchip),
772 GFP_KERNEL);
773 if (!girq->chip)
774 return -ENOMEM;
775 girq->parent_handler = sgpio_irq_handler;
776 girq->num_parents = 1;
777 girq->parents = devm_kcalloc(dev, 1,
778 sizeof(*girq->parents),
779 GFP_KERNEL);
780 if (!girq->parents)
781 return -ENOMEM;
782 girq->parents[0] = irq;
783 girq->default_type = IRQ_TYPE_NONE;
784 girq->handler = handle_bad_irq;
785
786 /* Disable all individual pins */
787 for (i = 0; i < SGPIO_MAX_BITS; i++)
788 sgpio_writel(priv, 0, REG_INT_ENABLE, i);
789 /* Master enable */
790 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA);
791 }
792 }
793
611 ret = devm_gpiochip_add_data(dev, gc, bank);
612 if (ret)
613 dev_err(dev, "Failed to register: ret %d\n", ret);
614
615 return ret;
616}
617
618static int microchip_sgpio_probe(struct platform_device *pdev)

--- 91 unchanged lines hidden --- 		794 ret = devm_gpiochip_add_data(dev, gc, bank);
795 if (ret)
796 dev_err(dev, "Failed to register: ret %d\n", ret);
797
798 return ret;
799}
800
801static int microchip_sgpio_probe(struct platform_device *pdev)

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