pinctrl-gemini.c (d0300e5e8d2fb74852f8116f26546e12cfa66735) pinctrl-gemini.c (ad63da85f45fa55c270e5681e9b985605ec51f8d)
1/*
2 * Driver for the Gemini pin controller
3 *
4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
5 *
6 * This is a group-only pin controller.
7 */
8#include <linux/err.h>

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62 * struct gemini_pin_group - describes a Gemini pin group
63 * @name: the name of this specific pin group
64 * @pins: an array of discrete physical pins used in this group, taken
65 * from the driver-local pin enumeration space
66 * @num_pins: the number of pins in this group array, i.e. the number of
67 * elements in .pins so we can iterate over that array
68 * @mask: bits to clear to enable this when doing pin muxing
69 * @value: bits to set to enable this when doing pin muxing
1/*
2 * Driver for the Gemini pin controller
3 *
4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
5 *
6 * This is a group-only pin controller.
7 */
8#include <linux/err.h>

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62 * struct gemini_pin_group - describes a Gemini pin group
63 * @name: the name of this specific pin group
64 * @pins: an array of discrete physical pins used in this group, taken
65 * from the driver-local pin enumeration space
66 * @num_pins: the number of pins in this group array, i.e. the number of
67 * elements in .pins so we can iterate over that array
68 * @mask: bits to clear to enable this when doing pin muxing
69 * @value: bits to set to enable this when doing pin muxing
70 * @driving_mask: bitmask for the IO Pad driving register for this
71 * group, if it supports altering the driving strength of
72 * its lines.
70 */
71struct gemini_pin_group {
72 const char *name;
73 const unsigned int *pins;
74 const unsigned int num_pins;
75 u32 mask;
76 u32 value;
73 */
74struct gemini_pin_group {
75 const char *name;
76 const unsigned int *pins;
77 const unsigned int num_pins;
78 u32 mask;
79 u32 value;
80 u32 driving_mask;
77};
78
79/* Some straight-forward control registers */
80#define GLOBAL_WORD_ID 0x00
81#define GLOBAL_STATUS 0x04
82#define GLOBAL_STATUS_FLPIN BIT(20)
81};
82
83/* Some straight-forward control registers */
84#define GLOBAL_WORD_ID 0x00
85#define GLOBAL_STATUS 0x04
86#define GLOBAL_STATUS_FLPIN BIT(20)
87#define GLOBAL_IODRIVE 0x10
83#define GLOBAL_GMAC_CTRL_SKEW 0x1c
84#define GLOBAL_GMAC0_DATA_SKEW 0x20
85#define GLOBAL_GMAC1_DATA_SKEW 0x24
86/*
87 * Global Miscellaneous Control Register
88 * This register controls all Gemini pad/pin multiplexing
89 *
90 * It is a tricky register though:

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733 },
734 {
735 .name = "idegrp",
736 .pins = ide_3512_pins,
737 .num_pins = ARRAY_SIZE(ide_3512_pins),
738 /* Conflict with all flash usage */
739 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
740 PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
88#define GLOBAL_GMAC_CTRL_SKEW 0x1c
89#define GLOBAL_GMAC0_DATA_SKEW 0x20
90#define GLOBAL_GMAC1_DATA_SKEW 0x24
91/*
92 * Global Miscellaneous Control Register
93 * This register controls all Gemini pad/pin multiplexing
94 *
95 * It is a tricky register though:

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738 },
739 {
740 .name = "idegrp",
741 .pins = ide_3512_pins,
742 .num_pins = ARRAY_SIZE(ide_3512_pins),
743 /* Conflict with all flash usage */
744 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
745 PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
746 .driving_mask = GENMASK(21, 20),
741 },
742 {
743 .name = "satagrp",
744 .pins = sata_3512_pins,
745 .num_pins = ARRAY_SIZE(sata_3512_pins),
746 },
747 {
748 .name = "usbgrp",
749 .pins = usb_3512_pins,
750 .num_pins = ARRAY_SIZE(usb_3512_pins),
751 },
752 {
753 .name = "gmii_gmac0_grp",
754 .pins = gmii_gmac0_3512_pins,
755 .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
747 },
748 {
749 .name = "satagrp",
750 .pins = sata_3512_pins,
751 .num_pins = ARRAY_SIZE(sata_3512_pins),
752 },
753 {
754 .name = "usbgrp",
755 .pins = usb_3512_pins,
756 .num_pins = ARRAY_SIZE(usb_3512_pins),
757 },
758 {
759 .name = "gmii_gmac0_grp",
760 .pins = gmii_gmac0_3512_pins,
761 .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
762 .driving_mask = GENMASK(17, 16),
756 },
757 {
758 .name = "gmii_gmac1_grp",
759 .pins = gmii_gmac1_3512_pins,
760 .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
761 /* Bring out RGMII on the GMAC1 pins */
762 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
763 },
764 {
765 .name = "gmii_gmac1_grp",
766 .pins = gmii_gmac1_3512_pins,
767 .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
768 /* Bring out RGMII on the GMAC1 pins */
769 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
770 .driving_mask = GENMASK(19, 18),
763 },
764 {
765 .name = "pcigrp",
766 .pins = pci_3512_pins,
767 .num_pins = ARRAY_SIZE(pci_3512_pins),
768 /* Conflict only with GPIO2 */
769 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
771 },
772 {
773 .name = "pcigrp",
774 .pins = pci_3512_pins,
775 .num_pins = ARRAY_SIZE(pci_3512_pins),
776 /* Conflict only with GPIO2 */
777 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
778 .driving_mask = GENMASK(23, 22),
770 },
771 {
772 .name = "lpcgrp",
773 .pins = lpc_3512_pins,
774 .num_pins = ARRAY_SIZE(lpc_3512_pins),
775 /* Conflict with SSP and UART modem pins */
776 .mask = SSP_PADS_ENABLE,
777 .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,

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1666 },
1667 {
1668 .name = "idegrp",
1669 .pins = ide_3516_pins,
1670 .num_pins = ARRAY_SIZE(ide_3516_pins),
1671 /* Conflict with all flash usage */
1672 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
1673 PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
779 },
780 {
781 .name = "lpcgrp",
782 .pins = lpc_3512_pins,
783 .num_pins = ARRAY_SIZE(lpc_3512_pins),
784 /* Conflict with SSP and UART modem pins */
785 .mask = SSP_PADS_ENABLE,
786 .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,

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1675 },
1676 {
1677 .name = "idegrp",
1678 .pins = ide_3516_pins,
1679 .num_pins = ARRAY_SIZE(ide_3516_pins),
1680 /* Conflict with all flash usage */
1681 .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE |
1682 PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE,
1683 .driving_mask = GENMASK(21, 20),
1674 },
1675 {
1676 .name = "satagrp",
1677 .pins = sata_3516_pins,
1678 .num_pins = ARRAY_SIZE(sata_3516_pins),
1679 },
1680 {
1681 .name = "usbgrp",
1682 .pins = usb_3516_pins,
1683 .num_pins = ARRAY_SIZE(usb_3516_pins),
1684 },
1685 {
1686 .name = "gmii_gmac0_grp",
1687 .pins = gmii_gmac0_3516_pins,
1688 .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
1684 },
1685 {
1686 .name = "satagrp",
1687 .pins = sata_3516_pins,
1688 .num_pins = ARRAY_SIZE(sata_3516_pins),
1689 },
1690 {
1691 .name = "usbgrp",
1692 .pins = usb_3516_pins,
1693 .num_pins = ARRAY_SIZE(usb_3516_pins),
1694 },
1695 {
1696 .name = "gmii_gmac0_grp",
1697 .pins = gmii_gmac0_3516_pins,
1698 .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
1699 .driving_mask = GENMASK(17, 16),
1689 },
1690 {
1691 .name = "gmii_gmac1_grp",
1692 .pins = gmii_gmac1_3516_pins,
1693 .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
1694 /* Bring out RGMII on the GMAC1 pins */
1695 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
1700 },
1701 {
1702 .name = "gmii_gmac1_grp",
1703 .pins = gmii_gmac1_3516_pins,
1704 .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
1705 /* Bring out RGMII on the GMAC1 pins */
1706 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
1707 .driving_mask = GENMASK(19, 18),
1696 },
1697 {
1698 .name = "pcigrp",
1699 .pins = pci_3516_pins,
1700 .num_pins = ARRAY_SIZE(pci_3516_pins),
1701 /* Conflict only with GPIO2 */
1702 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
1708 },
1709 {
1710 .name = "pcigrp",
1711 .pins = pci_3516_pins,
1712 .num_pins = ARRAY_SIZE(pci_3516_pins),
1713 /* Conflict only with GPIO2 */
1714 .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE,
1715 .driving_mask = GENMASK(23, 22),
1703 },
1704 {
1705 .name = "lpcgrp",
1706 .pins = lpc_3516_pins,
1707 .num_pins = ARRAY_SIZE(lpc_3516_pins),
1708 /* Conflict with SSP */
1709 .mask = SSP_PADS_ENABLE,
1710 .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,

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2010static const char * const uartgrps[] = { "uartrxtxgrp", "uartmodemgrp" };
2011static const char * const tvcgrps[] = { "tvcgrp" };
2012static const char * const nflashgrps[] = { "nflashgrp" };
2013static const char * const pflashgrps[] = { "pflashgrp", "pflashextgrp" };
2014static const char * const sflashgrps[] = { "sflashgrp" };
2015static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp",
2016 "gpio0dgrp", "gpio0egrp", "gpio0fgrp",
2017 "gpio0ggrp", "gpio0hgrp", "gpio0igrp",
1716 },
1717 {
1718 .name = "lpcgrp",
1719 .pins = lpc_3516_pins,
1720 .num_pins = ARRAY_SIZE(lpc_3516_pins),
1721 /* Conflict with SSP */
1722 .mask = SSP_PADS_ENABLE,
1723 .value = LPC_PADS_ENABLE | LPC_CLK_PAD_ENABLE,

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2023static const char * const uartgrps[] = { "uartrxtxgrp", "uartmodemgrp" };
2024static const char * const tvcgrps[] = { "tvcgrp" };
2025static const char * const nflashgrps[] = { "nflashgrp" };
2026static const char * const pflashgrps[] = { "pflashgrp", "pflashextgrp" };
2027static const char * const sflashgrps[] = { "sflashgrp" };
2028static const char * const gpio0grps[] = { "gpio0agrp", "gpio0bgrp", "gpio0cgrp",
2029 "gpio0dgrp", "gpio0egrp", "gpio0fgrp",
2030 "gpio0ggrp", "gpio0hgrp", "gpio0igrp",
2018 "gpio0jgrp", "gpio0kgrp" };
2031 "gpio0jgrp", "gpio0kgrp", "gpio0lgrp",
2032 "gpio0mgrp" };
2019static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp",
2020 "gpio1dgrp" };
2021static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" };
2022
2023static const struct gemini_pmx_func gemini_pmx_functions[] = {
2024 {
2025 .name = "dram",
2026 .groups = dramgrps,

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2317
2318static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx,
2319 unsigned int pin)
2320{
2321 const struct gemini_pin_conf *retconf;
2322 int i;
2323
2324 for (i = 0; i < pmx->nconfs; i++) {
2033static const char * const gpio1grps[] = { "gpio1agrp", "gpio1bgrp", "gpio1cgrp",
2034 "gpio1dgrp" };
2035static const char * const gpio2grps[] = { "gpio2agrp", "gpio2bgrp", "gpio2cgrp" };
2036
2037static const struct gemini_pmx_func gemini_pmx_functions[] = {
2038 {
2039 .name = "dram",
2040 .groups = dramgrps,

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2331
2332static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx,
2333 unsigned int pin)
2334{
2335 const struct gemini_pin_conf *retconf;
2336 int i;
2337
2338 for (i = 0; i < pmx->nconfs; i++) {
2325 retconf = &pmx->confs[i];
2339 retconf = &gemini_confs_3516[i];
2326 if (retconf->pin == pin)
2327 return retconf;
2328 }
2329 return NULL;
2330}
2331
2332static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2333 unsigned long *config)

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2388 dev_err(pmx->dev, "Invalid config param %04x\n", param);
2389 return -ENOTSUPP;
2390 }
2391 }
2392
2393 return ret;
2394}
2395
2340 if (retconf->pin == pin)
2341 return retconf;
2342 }
2343 return NULL;
2344}
2345
2346static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2347 unsigned long *config)

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2402 dev_err(pmx->dev, "Invalid config param %04x\n", param);
2403 return -ENOTSUPP;
2404 }
2405 }
2406
2407 return ret;
2408}
2409
2410static int gemini_pinconf_group_set(struct pinctrl_dev *pctldev,
2411 unsigned selector,
2412 unsigned long *configs,
2413 unsigned num_configs)
2414{
2415 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
2416 const struct gemini_pin_group *grp = NULL;
2417 enum pin_config_param param;
2418 u32 arg;
2419 u32 val;
2420 int i;
2421
2422 if (pmx->is_3512)
2423 grp = &gemini_3512_pin_groups[selector];
2424 if (pmx->is_3516)
2425 grp = &gemini_3516_pin_groups[selector];
2426
2427 /* First figure out if this group supports configs */
2428 if (!grp->driving_mask) {
2429 dev_err(pmx->dev, "pin config group \"%s\" does "
2430 "not support drive strength setting\n",
2431 grp->name);
2432 return -EINVAL;
2433 }
2434
2435 for (i = 0; i < num_configs; i++) {
2436 param = pinconf_to_config_param(configs[i]);
2437 arg = pinconf_to_config_argument(configs[i]);
2438
2439 switch (param) {
2440 case PIN_CONFIG_DRIVE_STRENGTH:
2441 switch (arg) {
2442 case 4:
2443 val = 0;
2444 break;
2445 case 8:
2446 val = 1;
2447 break;
2448 case 12:
2449 val = 2;
2450 break;
2451 case 16:
2452 val = 3;
2453 break;
2454 default:
2455 dev_err(pmx->dev,
2456 "invalid drive strength %d mA\n",
2457 arg);
2458 return -ENOTSUPP;
2459 }
2460 val <<= (ffs(grp->driving_mask) - 1);
2461 regmap_update_bits(pmx->map, GLOBAL_IODRIVE,
2462 grp->driving_mask,
2463 val);
2464 dev_info(pmx->dev,
2465 "set group %s to %d mA drive strength mask %08x val %08x\n",
2466 grp->name, arg, grp->driving_mask, val);
2467 break;
2468 default:
2469 dev_err(pmx->dev, "invalid config param %04x\n", param);
2470 return -ENOTSUPP;
2471 }
2472 }
2473
2474 return 0;
2475}
2476
2396static const struct pinconf_ops gemini_pinconf_ops = {
2397 .pin_config_get = gemini_pinconf_get,
2398 .pin_config_set = gemini_pinconf_set,
2477static const struct pinconf_ops gemini_pinconf_ops = {
2478 .pin_config_get = gemini_pinconf_get,
2479 .pin_config_set = gemini_pinconf_set,
2480 .pin_config_group_set = gemini_pinconf_group_set,
2399 .is_generic = true,
2400};
2401
2402static struct pinctrl_desc gemini_pmx_desc = {
2403 .name = DRIVER_NAME,
2404 .pctlops = &gemini_pctrl_ops,
2405 .pmxops = &gemini_pmx_ops,
2406 .confops = &gemini_pinconf_ops,

--- 106 unchanged lines hidden --- 		2481 .is_generic = true,
2482};
2483
2484static struct pinctrl_desc gemini_pmx_desc = {
2485 .name = DRIVER_NAME,
2486 .pctlops = &gemini_pctrl_ops,
2487 .pmxops = &gemini_pmx_ops,
2488 .confops = &gemini_pinconf_ops,

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