pinctrl-dove.c (b7d3622a39fde7658170b7f3cf6c6889bb8db30d) pinctrl-dove.c (3c7d563789241442abfaeb0574ed4f93f8fcdebe)
1/*
2 * Marvell Dove pinctrl driver based on mvebu pinctrl core
3 *
4 * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or

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13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/bitops.h>
17#include <linux/platform_device.h>
18#include <linux/clk.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
1/*
2 * Marvell Dove pinctrl driver based on mvebu pinctrl core
3 *
4 * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or

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13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/bitops.h>
17#include <linux/platform_device.h>
18#include <linux/clk.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/mfd/syscon.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/regmap.h>
22
23#include "pinctrl-mvebu.h"
24
24
25#include "pinctrl-mvebu.h"
26
25#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000)
26#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
27#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
28#define DOVE_AU0_AC97_SEL BIT(16)
29#define DOVE_PMU_SIGNAL_SELECT_0 (DOVE_SB_REGS_VIRT_BASE + 0xd802C)
30#define DOVE_PMU_SIGNAL_SELECT_1 (DOVE_SB_REGS_VIRT_BASE + 0xd8030)
31#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
32#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
33#define DOVE_TWSI_ENABLE_OPTION1 BIT(7)
34#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
35#define DOVE_TWSI_ENABLE_OPTION2 BIT(20)
36#define DOVE_TWSI_ENABLE_OPTION3 BIT(21)
37#define DOVE_TWSI_OPTION3_GPIO BIT(22)
38#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
39#define DOVE_SSP_ON_AU1 BIT(0)
40#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
41#define DOVE_AU1_SPDIFO_GPIO_EN BIT(1)
42#define DOVE_NAND_GPIO_EN BIT(0)
43#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
44#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
45#define DOVE_SPI_GPIO_SEL BIT(5)
46#define DOVE_UART1_GPIO_SEL BIT(4)
47#define DOVE_AU1_GPIO_SEL BIT(3)
48#define DOVE_CAM_GPIO_SEL BIT(2)
49#define DOVE_SD1_GPIO_SEL BIT(1)
50#define DOVE_SD0_GPIO_SEL BIT(0)
27/* Internal registers can be configured at any 1 MiB aligned address */
28#define INT_REGS_MASK ~(SZ_1M - 1)
29#define MPP4_REGS_OFFS 0xd0440
30#define PMU_REGS_OFFS 0xd802c
31#define GC_REGS_OFFS 0xe802c
51
32
52#define MPPS_PER_REG 8
53#define MPP_BITS 4
54#define MPP_MASK 0xf
33/* MPP Base registers */
34#define PMU_MPP_GENERAL_CTRL 0x10
35#define AU0_AC97_SEL BIT(16)
55
36
37/* MPP Control 4 register */
38#define SPI_GPIO_SEL BIT(5)
39#define UART1_GPIO_SEL BIT(4)
40#define AU1_GPIO_SEL BIT(3)
41#define CAM_GPIO_SEL BIT(2)
42#define SD1_GPIO_SEL BIT(1)
43#define SD0_GPIO_SEL BIT(0)
44
45/* PMU Signal Select registers */
46#define PMU_SIGNAL_SELECT_0 0x00
47#define PMU_SIGNAL_SELECT_1 0x04
48
49/* Global Config regmap registers */
50#define GLOBAL_CONFIG_1 0x00
51#define TWSI_ENABLE_OPTION1 BIT(7)
52#define GLOBAL_CONFIG_2 0x04
53#define TWSI_ENABLE_OPTION2 BIT(20)
54#define TWSI_ENABLE_OPTION3 BIT(21)
55#define TWSI_OPTION3_GPIO BIT(22)
56#define SSP_CTRL_STATUS_1 0x08
57#define SSP_ON_AU1 BIT(0)
58#define MPP_GENERAL_CONFIG 0x10
59#define AU1_SPDIFO_GPIO_EN BIT(1)
60#define NAND_GPIO_EN BIT(0)
61
56#define CONFIG_PMU BIT(4)
57
62#define CONFIG_PMU BIT(4)
63
58static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
59 unsigned long *config)
64static void __iomem *mpp_base;
65static void __iomem *mpp4_base;
66static void __iomem *pmu_base;
67static struct regmap *gconfmap;
68
69static int dove_mpp_ctrl_get(unsigned pid, unsigned long *config)
60{
70{
61 unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS;
62 unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS;
63 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
71 return default_mpp_ctrl_get(mpp_base, pid, config);
72}
73
74static int dove_mpp_ctrl_set(unsigned pid, unsigned long config)
75{
76 return default_mpp_ctrl_set(mpp_base, pid, config);
77}
78
79static int dove_pmu_mpp_ctrl_get(unsigned pid, unsigned long *config)
80{
81 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
82 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
83 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL);
64 unsigned long func;
65
84 unsigned long func;
85
66 if (pmu & (1 << ctrl->pid)) {
67 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off);
68 *config = (func >> shift) & MPP_MASK;
69 *config |= CONFIG_PMU;
70 } else {
71 func = readl(DOVE_MPP_VIRT_BASE + off);
72 *config = (func >> shift) & MPP_MASK;
73 }
86 if ((pmu & BIT(pid)) == 0)
87 return default_mpp_ctrl_get(mpp_base, pid, config);
88
89 func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
90 *config = (func >> shift) & MVEBU_MPP_MASK;
91 *config |= CONFIG_PMU;
92
74 return 0;
75}
76
93 return 0;
94}
95
77static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
78 unsigned long config)
96static int dove_pmu_mpp_ctrl_set(unsigned pid, unsigned long config)
79{
97{
80 unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS;
81 unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS;
82 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
98 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
99 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
100 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL);
83 unsigned long func;
84
101 unsigned long func;
102
85 if (config & CONFIG_PMU) {
86 writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
87 func = readl(DOVE_PMU_SIGNAL_SELECT_0 + off);
88 func &= ~(MPP_MASK << shift);
89 func |= (config & MPP_MASK) << shift;
90 writel(func, DOVE_PMU_SIGNAL_SELECT_0 + off);
91 } else {
92 writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
93 func = readl(DOVE_MPP_VIRT_BASE + off);
94 func &= ~(MPP_MASK << shift);
95 func |= (config & MPP_MASK) << shift;
96 writel(func, DOVE_MPP_VIRT_BASE + off);
103 if ((config & CONFIG_PMU) == 0) {
104 writel(pmu & ~BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL);
105 return default_mpp_ctrl_set(mpp_base, pid, config);
97 }
106 }
107
108 writel(pmu | BIT(pid), mpp_base + PMU_MPP_GENERAL_CTRL);
109 func = readl(pmu_base + PMU_SIGNAL_SELECT_0 + off);
110 func &= ~(MVEBU_MPP_MASK << shift);
111 func |= (config & MVEBU_MPP_MASK) << shift;
112 writel(func, pmu_base + PMU_SIGNAL_SELECT_0 + off);
113
98 return 0;
99}
100
114 return 0;
115}
116
101static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
102 unsigned long *config)
117static int dove_mpp4_ctrl_get(unsigned pid, unsigned long *config)
103{
118{
104 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
119 unsigned long mpp4 = readl(mpp4_base);
105 unsigned long mask;
106
120 unsigned long mask;
121
107 switch (ctrl->pid) {
122 switch (pid) {
108 case 24: /* mpp_camera */
123 case 24: /* mpp_camera */
109 mask = DOVE_CAM_GPIO_SEL;
124 mask = CAM_GPIO_SEL;
110 break;
111 case 40: /* mpp_sdio0 */
125 break;
126 case 40: /* mpp_sdio0 */
112 mask = DOVE_SD0_GPIO_SEL;
127 mask = SD0_GPIO_SEL;
113 break;
114 case 46: /* mpp_sdio1 */
128 break;
129 case 46: /* mpp_sdio1 */
115 mask = DOVE_SD1_GPIO_SEL;
130 mask = SD1_GPIO_SEL;
116 break;
117 case 58: /* mpp_spi0 */
131 break;
132 case 58: /* mpp_spi0 */
118 mask = DOVE_SPI_GPIO_SEL;
133 mask = SPI_GPIO_SEL;
119 break;
120 case 62: /* mpp_uart1 */
134 break;
135 case 62: /* mpp_uart1 */
121 mask = DOVE_UART1_GPIO_SEL;
136 mask = UART1_GPIO_SEL;
122 break;
123 default:
124 return -EINVAL;
125 }
126
127 *config = ((mpp4 & mask) != 0);
128
129 return 0;
130}
131
137 break;
138 default:
139 return -EINVAL;
140 }
141
142 *config = ((mpp4 & mask) != 0);
143
144 return 0;
145}
146
132static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
133 unsigned long config)
147static int dove_mpp4_ctrl_set(unsigned pid, unsigned long config)
134{
148{
135 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
149 unsigned long mpp4 = readl(mpp4_base);
136 unsigned long mask;
137
150 unsigned long mask;
151
138 switch (ctrl->pid) {
152 switch (pid) {
139 case 24: /* mpp_camera */
153 case 24: /* mpp_camera */
140 mask = DOVE_CAM_GPIO_SEL;
154 mask = CAM_GPIO_SEL;
141 break;
142 case 40: /* mpp_sdio0 */
155 break;
156 case 40: /* mpp_sdio0 */
143 mask = DOVE_SD0_GPIO_SEL;
157 mask = SD0_GPIO_SEL;
144 break;
145 case 46: /* mpp_sdio1 */
158 break;
159 case 46: /* mpp_sdio1 */
146 mask = DOVE_SD1_GPIO_SEL;
160 mask = SD1_GPIO_SEL;
147 break;
148 case 58: /* mpp_spi0 */
161 break;
162 case 58: /* mpp_spi0 */
149 mask = DOVE_SPI_GPIO_SEL;
163 mask = SPI_GPIO_SEL;
150 break;
151 case 62: /* mpp_uart1 */
164 break;
165 case 62: /* mpp_uart1 */
152 mask = DOVE_UART1_GPIO_SEL;
166 mask = UART1_GPIO_SEL;
153 break;
154 default:
155 return -EINVAL;
156 }
157
158 mpp4 &= ~mask;
159 if (config)
160 mpp4 |= mask;
161
167 break;
168 default:
169 return -EINVAL;
170 }
171
172 mpp4 &= ~mask;
173 if (config)
174 mpp4 |= mask;
175
162 writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
176 writel(mpp4, mpp4_base);
163
164 return 0;
165}
166
177
178 return 0;
179}
180
167static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
168 unsigned long *config)
181static int dove_nand_ctrl_get(unsigned pid, unsigned long *config)
169{
182{
170 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
183 unsigned int gmpp;
171
184
172 *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0);
185 regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
186 *config = ((gmpp & NAND_GPIO_EN) != 0);
173
174 return 0;
175}
176
187
188 return 0;
189}
190
177static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
178 unsigned long config)
191static int dove_nand_ctrl_set(unsigned pid, unsigned long config)
179{
192{
180 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
181
182 gmpp &= ~DOVE_NAND_GPIO_EN;
183 if (config)
184 gmpp |= DOVE_NAND_GPIO_EN;
185
186 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
187
193 regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
194 NAND_GPIO_EN,
195 (config) ? NAND_GPIO_EN : 0);
188 return 0;
189}
190
196 return 0;
197}
198
191static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
192 unsigned long *config)
199static int dove_audio0_ctrl_get(unsigned pid, unsigned long *config)
193{
200{
194 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
201 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL);
195
202
196 *config = ((pmu & DOVE_AU0_AC97_SEL) != 0);
203 *config = ((pmu & AU0_AC97_SEL) != 0);
197
198 return 0;
199}
200
204
205 return 0;
206}
207
201static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
202 unsigned long config)
208static int dove_audio0_ctrl_set(unsigned pid, unsigned long config)
203{
209{
204 unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
210 unsigned long pmu = readl(mpp_base + PMU_MPP_GENERAL_CTRL);
205
211
206 pmu &= ~DOVE_AU0_AC97_SEL;
212 pmu &= ~AU0_AC97_SEL;
207 if (config)
213 if (config)
208 pmu |= DOVE_AU0_AC97_SEL;
209 writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL);
214 pmu |= AU0_AC97_SEL;
215 writel(pmu, mpp_base + PMU_MPP_GENERAL_CTRL);
210
211 return 0;
212}
213
216
217 return 0;
218}
219
214static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
215 unsigned long *config)
220static int dove_audio1_ctrl_get(unsigned pid, unsigned long *config)
216{
221{
217 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
218 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
219 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
220 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
222 unsigned int mpp4 = readl(mpp4_base);
223 unsigned int sspc1;
224 unsigned int gmpp;
225 unsigned int gcfg2;
221
226
227 regmap_read(gconfmap, SSP_CTRL_STATUS_1, &sspc1);
228 regmap_read(gconfmap, MPP_GENERAL_CONFIG, &gmpp);
229 regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
230
222 *config = 0;
231 *config = 0;
223 if (mpp4 & DOVE_AU1_GPIO_SEL)
232 if (mpp4 & AU1_GPIO_SEL)
224 *config |= BIT(3);
233 *config |= BIT(3);
225 if (sspc1 & DOVE_SSP_ON_AU1)
234 if (sspc1 & SSP_ON_AU1)
226 *config |= BIT(2);
235 *config |= BIT(2);
227 if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN)
236 if (gmpp & AU1_SPDIFO_GPIO_EN)
228 *config |= BIT(1);
237 *config |= BIT(1);
229 if (gcfg2 & DOVE_TWSI_OPTION3_GPIO)
238 if (gcfg2 & TWSI_OPTION3_GPIO)
230 *config |= BIT(0);
231
232 /* SSP/TWSI only if I2S1 not set*/
233 if ((*config & BIT(3)) == 0)
234 *config &= ~(BIT(2) | BIT(0));
235 /* TWSI only if SPDIFO not set*/
236 if ((*config & BIT(1)) == 0)
237 *config &= ~BIT(0);
238 return 0;
239}
240
239 *config |= BIT(0);
240
241 /* SSP/TWSI only if I2S1 not set*/
242 if ((*config & BIT(3)) == 0)
243 *config &= ~(BIT(2) | BIT(0));
244 /* TWSI only if SPDIFO not set*/
245 if ((*config & BIT(1)) == 0)
246 *config &= ~BIT(0);
247 return 0;
248}
249
241static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
242 unsigned long config)
250static int dove_audio1_ctrl_set(unsigned pid, unsigned long config)
243{
251{
244 unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
245 unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
246 unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
247 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
252 unsigned int mpp4 = readl(mpp4_base);
248
253
249 /*
250 * clear all audio1 related bits before configure
251 */
252 gcfg2 &= ~DOVE_TWSI_OPTION3_GPIO;
253 gmpp &= ~DOVE_AU1_SPDIFO_GPIO_EN;
254 sspc1 &= ~DOVE_SSP_ON_AU1;
255 mpp4 &= ~DOVE_AU1_GPIO_SEL;
256
257 if (config & BIT(0))
258 gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
259 if (config & BIT(1))
260 gmpp |= DOVE_AU1_SPDIFO_GPIO_EN;
261 if (config & BIT(2))
262 sspc1 |= DOVE_SSP_ON_AU1;
254 mpp4 &= ~AU1_GPIO_SEL;
263 if (config & BIT(3))
255 if (config & BIT(3))
264 mpp4 |= DOVE_AU1_GPIO_SEL;
256 mpp4 |= AU1_GPIO_SEL;
257 writel(mpp4, mpp4_base);
265
258
266 writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
267 writel(sspc1, DOVE_SSP_CTRL_STATUS_1);
268 writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
269 writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
259 regmap_update_bits(gconfmap, SSP_CTRL_STATUS_1,
260 SSP_ON_AU1,
261 (config & BIT(2)) ? SSP_ON_AU1 : 0);
262 regmap_update_bits(gconfmap, MPP_GENERAL_CONFIG,
263 AU1_SPDIFO_GPIO_EN,
264 (config & BIT(1)) ? AU1_SPDIFO_GPIO_EN : 0);
265 regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
266 TWSI_OPTION3_GPIO,
267 (config & BIT(0)) ? TWSI_OPTION3_GPIO : 0);
270
271 return 0;
272}
273
274/* mpp[52:57] gpio pins depend heavily on current config;
275 * gpio_req does not try to mux in gpio capabilities to not
276 * break other functions. If you require all mpps as gpio
277 * enforce gpio setting by pinctrl mapping.
278 */
268
269 return 0;
270}
271
272/* mpp[52:57] gpio pins depend heavily on current config;
273 * gpio_req does not try to mux in gpio capabilities to not
274 * break other functions. If you require all mpps as gpio
275 * enforce gpio setting by pinctrl mapping.
276 */
279static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid)
277static int dove_audio1_ctrl_gpio_req(unsigned pid)
280{
281 unsigned long config;
282
278{
279 unsigned long config;
280
283 dove_audio1_ctrl_get(ctrl, &config);
281 dove_audio1_ctrl_get(pid, &config);
284
285 switch (config) {
286 case 0x02: /* i2s1 : gpio[56:57] */
287 case 0x0e: /* ssp : gpio[56:57] */
288 if (pid >= 56)
289 return 0;
290 return -ENOTSUPP;
291 case 0x08: /* spdifo : gpio[52:55] */

--- 6 unchanged lines hidden (view full) ---

298 /* 0x00 : i2s1/spdifo : no gpio */
299 /* 0x0c : ssp/spdifo : no gpio */
300 /* 0x0f : ssp/twsi : no gpio */
301 }
302 return -ENOTSUPP;
303}
304
305/* mpp[52:57] has gpio pins capable of in and out */
282
283 switch (config) {
284 case 0x02: /* i2s1 : gpio[56:57] */
285 case 0x0e: /* ssp : gpio[56:57] */
286 if (pid >= 56)
287 return 0;
288 return -ENOTSUPP;
289 case 0x08: /* spdifo : gpio[52:55] */

--- 6 unchanged lines hidden (view full) ---

296 /* 0x00 : i2s1/spdifo : no gpio */
297 /* 0x0c : ssp/spdifo : no gpio */
298 /* 0x0f : ssp/twsi : no gpio */
299 }
300 return -ENOTSUPP;
301}
302
303/* mpp[52:57] has gpio pins capable of in and out */
306static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid,
307 bool input)
304static int dove_audio1_ctrl_gpio_dir(unsigned pid, bool input)
308{
309 if (pid < 52 || pid > 57)
310 return -ENOTSUPP;
311 return 0;
312}
313
305{
306 if (pid < 52 || pid > 57)
307 return -ENOTSUPP;
308 return 0;
309}
310
314static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
315 unsigned long *config)
311static int dove_twsi_ctrl_get(unsigned pid, unsigned long *config)
316{
312{
317 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
318 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
313 unsigned int gcfg1;
314 unsigned int gcfg2;
319
315
316 regmap_read(gconfmap, GLOBAL_CONFIG_1, &gcfg1);
317 regmap_read(gconfmap, GLOBAL_CONFIG_2, &gcfg2);
318
320 *config = 0;
319 *config = 0;
321 if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1)
320 if (gcfg1 & TWSI_ENABLE_OPTION1)
322 *config = 1;
321 *config = 1;
323 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2)
322 else if (gcfg2 & TWSI_ENABLE_OPTION2)
324 *config = 2;
323 *config = 2;
325 else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3)
324 else if (gcfg2 & TWSI_ENABLE_OPTION3)
326 *config = 3;
327
328 return 0;
329}
330
325 *config = 3;
326
327 return 0;
328}
329
331static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
332 unsigned long config)
330static int dove_twsi_ctrl_set(unsigned pid, unsigned long config)
333{
331{
334 unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
335 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
332 unsigned int gcfg1 = 0;
333 unsigned int gcfg2 = 0;
336
334
337 gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1;
338 gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION3);
339
340 switch (config) {
341 case 1:
335 switch (config) {
336 case 1:
342 gcfg1 |= DOVE_TWSI_ENABLE_OPTION1;
337 gcfg1 = TWSI_ENABLE_OPTION1;
343 break;
344 case 2:
338 break;
339 case 2:
345 gcfg2 |= DOVE_TWSI_ENABLE_OPTION2;
340 gcfg2 = TWSI_ENABLE_OPTION2;
346 break;
347 case 3:
341 break;
342 case 3:
348 gcfg2 |= DOVE_TWSI_ENABLE_OPTION3;
343 gcfg2 = TWSI_ENABLE_OPTION3;
349 break;
350 }
351
344 break;
345 }
346
352 writel(gcfg1, DOVE_GLOBAL_CONFIG_1);
353 writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
347 regmap_update_bits(gconfmap, GLOBAL_CONFIG_1,
348 TWSI_ENABLE_OPTION1,
349 gcfg1);
350 regmap_update_bits(gconfmap, GLOBAL_CONFIG_2,
351 TWSI_ENABLE_OPTION2 | TWSI_ENABLE_OPTION3,
352 gcfg2);
354
355 return 0;
356}
357
358static struct mvebu_mpp_ctrl dove_mpp_controls[] = {
353
354 return 0;
355}
356
357static struct mvebu_mpp_ctrl dove_mpp_controls[] = {
359 MPP_FUNC_CTRL(0, 0, "mpp0", dove_pmu_mpp_ctrl),
360 MPP_FUNC_CTRL(1, 1, "mpp1", dove_pmu_mpp_ctrl),
361 MPP_FUNC_CTRL(2, 2, "mpp2", dove_pmu_mpp_ctrl),
362 MPP_FUNC_CTRL(3, 3, "mpp3", dove_pmu_mpp_ctrl),
363 MPP_FUNC_CTRL(4, 4, "mpp4", dove_pmu_mpp_ctrl),
364 MPP_FUNC_CTRL(5, 5, "mpp5", dove_pmu_mpp_ctrl),
365 MPP_FUNC_CTRL(6, 6, "mpp6", dove_pmu_mpp_ctrl),
366 MPP_FUNC_CTRL(7, 7, "mpp7", dove_pmu_mpp_ctrl),
367 MPP_FUNC_CTRL(8, 8, "mpp8", dove_pmu_mpp_ctrl),
368 MPP_FUNC_CTRL(9, 9, "mpp9", dove_pmu_mpp_ctrl),
369 MPP_FUNC_CTRL(10, 10, "mpp10", dove_pmu_mpp_ctrl),
370 MPP_FUNC_CTRL(11, 11, "mpp11", dove_pmu_mpp_ctrl),
371 MPP_FUNC_CTRL(12, 12, "mpp12", dove_pmu_mpp_ctrl),
372 MPP_FUNC_CTRL(13, 13, "mpp13", dove_pmu_mpp_ctrl),
373 MPP_FUNC_CTRL(14, 14, "mpp14", dove_pmu_mpp_ctrl),
374 MPP_FUNC_CTRL(15, 15, "mpp15", dove_pmu_mpp_ctrl),
375 MPP_REG_CTRL(16, 23),
358 MPP_FUNC_CTRL(0, 15, NULL, dove_pmu_mpp_ctrl),
359 MPP_FUNC_CTRL(16, 23, NULL, dove_mpp_ctrl),
376 MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl),
377 MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl),
378 MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl),
379 MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl),
380 MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl),
381 MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl),
382 MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl),
383 MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl),

--- 383 unchanged lines hidden (view full) ---

767
768static struct clk *clk;
769
770static struct of_device_id dove_pinctrl_of_match[] = {
771 { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info },
772 { }
773};
774
360 MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl),
361 MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl),
362 MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl),
363 MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl),
364 MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl),
365 MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl),
366 MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl),
367 MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl),

--- 383 unchanged lines hidden (view full) ---

751
752static struct clk *clk;
753
754static struct of_device_id dove_pinctrl_of_match[] = {
755 { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info },
756 { }
757};
758
759static struct regmap_config gc_regmap_config = {
760 .reg_bits = 32,
761 .val_bits = 32,
762 .reg_stride = 4,
763 .max_register = 5,
764};
765
775static int dove_pinctrl_probe(struct platform_device *pdev)
776{
766static int dove_pinctrl_probe(struct platform_device *pdev)
767{
768 struct resource *res, *mpp_res;
769 struct resource fb_res;
777 const struct of_device_id *match =
778 of_match_device(dove_pinctrl_of_match, &pdev->dev);
779 pdev->dev.platform_data = (void *)match->data;
780
781 /*
782 * General MPP Configuration Register is part of pdma registers.
783 * grab clk to make sure it is ticking.
784 */
785 clk = devm_clk_get(&pdev->dev, NULL);
786 if (IS_ERR(clk)) {
787 dev_err(&pdev->dev, "Unable to get pdma clock");
788 return PTR_ERR(clk);
789 }
790 clk_prepare_enable(clk);
791
770 const struct of_device_id *match =
771 of_match_device(dove_pinctrl_of_match, &pdev->dev);
772 pdev->dev.platform_data = (void *)match->data;
773
774 /*
775 * General MPP Configuration Register is part of pdma registers.
776 * grab clk to make sure it is ticking.
777 */
778 clk = devm_clk_get(&pdev->dev, NULL);
779 if (IS_ERR(clk)) {
780 dev_err(&pdev->dev, "Unable to get pdma clock");
781 return PTR_ERR(clk);
782 }
783 clk_prepare_enable(clk);
784
785 mpp_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
786 mpp_base = devm_ioremap_resource(&pdev->dev, mpp_res);
787 if (IS_ERR(mpp_base))
788 return PTR_ERR(mpp_base);
789
790 /* prepare fallback resource */
791 memcpy(&fb_res, mpp_res, sizeof(struct resource));
792 fb_res.start = 0;
793
794 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
795 if (!res) {
796 dev_warn(&pdev->dev, "falling back to hardcoded MPP4 resource\n");
797 adjust_resource(&fb_res,
798 (mpp_res->start & INT_REGS_MASK) + MPP4_REGS_OFFS, 0x4);
799 res = &fb_res;
800 }
801
802 mpp4_base = devm_ioremap_resource(&pdev->dev, res);
803 if (IS_ERR(mpp4_base))
804 return PTR_ERR(mpp4_base);
805
806 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
807 if (!res) {
808 dev_warn(&pdev->dev, "falling back to hardcoded PMU resource\n");
809 adjust_resource(&fb_res,
810 (mpp_res->start & INT_REGS_MASK) + PMU_REGS_OFFS, 0x8);
811 res = &fb_res;
812 }
813
814 pmu_base = devm_ioremap_resource(&pdev->dev, res);
815 if (IS_ERR(pmu_base))
816 return PTR_ERR(pmu_base);
817
818 gconfmap = syscon_regmap_lookup_by_compatible("marvell,dove-global-config");
819 if (IS_ERR(gconfmap)) {
820 void __iomem *gc_base;
821
822 dev_warn(&pdev->dev, "falling back to hardcoded global registers\n");
823 adjust_resource(&fb_res,
824 (mpp_res->start & INT_REGS_MASK) + GC_REGS_OFFS, 0x14);
825 gc_base = devm_ioremap_resource(&pdev->dev, &fb_res);
826 if (IS_ERR(gc_base))
827 return PTR_ERR(gc_base);
828 gconfmap = devm_regmap_init_mmio(&pdev->dev,
829 gc_base, &gc_regmap_config);
830 if (IS_ERR(gconfmap))
831 return PTR_ERR(gconfmap);
832 }
833
834 /* Warn on any missing DT resource */
835 if (fb_res.start)
836 dev_warn(&pdev->dev, FW_BUG "Missing pinctrl regs in DTB. Please update your firmware.\n");
837
792 return mvebu_pinctrl_probe(pdev);
793}
794
795static int dove_pinctrl_remove(struct platform_device *pdev)
796{
797 int ret;
798
799 ret = mvebu_pinctrl_remove(pdev);

--- 20 unchanged lines hidden --- 		838 return mvebu_pinctrl_probe(pdev);
839}
840
841static int dove_pinctrl_remove(struct platform_device *pdev)
842{
843 int ret;
844
845 ret = mvebu_pinctrl_remove(pdev);

--- 20 unchanged lines hidden ---