pinctrl-meson.c (1aaaa9acaea1dd2878d6c92b45e4c117ef425baf) pinctrl-meson.c (db80f0e158e62164308a857bce442dfeddb5c29e)
1/*
2 * Pin controller and GPIO driver for Amlogic Meson SoCs
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.

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16 * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and
17 * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
18 * variable number of pins.
19 *
20 * The AO bank is special because it belongs to the Always-On power
21 * domain which can't be powered off; the bank also uses a set of
22 * registers different from the other banks.
23 *
1/*
2 * Pin controller and GPIO driver for Amlogic Meson SoCs
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.

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16 * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and
17 * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
18 * variable number of pins.
19 *
20 * The AO bank is special because it belongs to the Always-On power
21 * domain which can't be powered off; the bank also uses a set of
22 * registers different from the other banks.
23 *
24 * For each of the two power domains (regular and always-on) there are
25 * 4 different register ranges that control the following properties
26 * of the pins:
24 * For each pin controller there are 4 different register ranges that
25 * control the following properties of the pins:
27 * 1) pin muxing
28 * 2) pull enable/disable
29 * 3) pull up/down
30 * 4) GPIO direction, output value, input value
31 *
32 * In some cases the register ranges for pull enable and pull
33 * direction are the same and thus there are only 3 register ranges.
34 *
35 * Every pinmux group can be enabled by a specific bit in the first
26 * 1) pin muxing
27 * 2) pull enable/disable
28 * 3) pull up/down
29 * 4) GPIO direction, output value, input value
30 *
31 * In some cases the register ranges for pull enable and pull
32 * direction are the same and thus there are only 3 register ranges.
33 *
34 * Every pinmux group can be enabled by a specific bit in the first
36 * register range of the domain; when all groups for a given pin are
37 * disabled the pin acts as a GPIO.
35 * register range; when all groups for a given pin are disabled the
36 * pin acts as a GPIO.
38 *
39 * For the pull and GPIO configuration every bank uses a contiguous
40 * set of bits in the register sets described above; the same register
41 * can be shared by more banks with different offsets.
42 *
43 * In addition to this there are some registers shared between all
44 * banks that control the IRQ functionality. This feature is not
45 * supported at the moment by the driver.

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61
62#include "../core.h"
63#include "../pinctrl-utils.h"
64#include "pinctrl-meson.h"
65
66/**
67 * meson_get_bank() - find the bank containing a given pin
68 *
37 *
38 * For the pull and GPIO configuration every bank uses a contiguous
39 * set of bits in the register sets described above; the same register
40 * can be shared by more banks with different offsets.
41 *
42 * In addition to this there are some registers shared between all
43 * banks that control the IRQ functionality. This feature is not
44 * supported at the moment by the driver.

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60
61#include "../core.h"
62#include "../pinctrl-utils.h"
63#include "pinctrl-meson.h"
64
65/**
66 * meson_get_bank() - find the bank containing a given pin
67 *
69 * @domain: the domain containing the pin
68 * @pc: the pinctrl instance
70 * @pin: the pin number
71 * @bank: the found bank
72 *
73 * Return: 0 on success, a negative value on error
74 */
69 * @pin: the pin number
70 * @bank: the found bank
71 *
72 * Return: 0 on success, a negative value on error
73 */
75static int meson_get_bank(struct meson_domain *domain, unsigned int pin,
74static int meson_get_bank(struct meson_pinctrl *pc, unsigned int pin,
76 struct meson_bank **bank)
77{
78 int i;
79
75 struct meson_bank **bank)
76{
77 int i;
78
80 for (i = 0; i < domain->data->num_banks; i++) {
81 if (pin >= domain->data->banks[i].first &&
82 pin <= domain->data->banks[i].last) {
83 *bank = &domain->data->banks[i];
79 for (i = 0; i < pc->data->num_banks; i++) {
80 if (pin >= pc->data->banks[i].first &&
81 pin <= pc->data->banks[i].last) {
82 *bank = &pc->data->banks[i];
84 return 0;
85 }
86 }
87
88 return -EINVAL;
89}
90
91/**
83 return 0;
84 }
85 }
86
87 return -EINVAL;
88}
89
90/**
92 * meson_get_domain_and_bank() - find domain and bank containing a given pin
93 *
94 * @pc: Meson pin controller device
95 * @pin: the pin number
96 * @domain: the found domain
97 * @bank: the found bank
98 *
99 * Return: 0 on success, a negative value on error
100 */
101static int meson_get_domain_and_bank(struct meson_pinctrl *pc, unsigned int pin,
102 struct meson_domain **domain,
103 struct meson_bank **bank)
104{
105 struct meson_domain *d;
106
107 d = pc->domain;
108
109 if (pin >= d->data->pin_base &&
110 pin < d->data->pin_base + d->data->num_pins) {
111 *domain = d;
112 return meson_get_bank(d, pin, bank);
113 }
114
115 return -EINVAL;
116}
117
118/**
119 * meson_calc_reg_and_bit() - calculate register and bit for a pin
120 *
121 * @bank: the bank containing the pin
122 * @pin: the pin number
123 * @reg_type: the type of register needed (pull-enable, pull, etc...)
124 * @reg: the computed register offset
125 * @bit: the computed bit
126 */

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185 * The function disables all pinmux groups using a pin except the
186 * selected one. If @sel_group is -1 all groups are disabled, leaving
187 * the pin in GPIO mode.
188 */
189static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc,
190 unsigned int pin, int sel_group)
191{
192 struct meson_pmx_group *group;
91 * meson_calc_reg_and_bit() - calculate register and bit for a pin
92 *
93 * @bank: the bank containing the pin
94 * @pin: the pin number
95 * @reg_type: the type of register needed (pull-enable, pull, etc...)
96 * @reg: the computed register offset
97 * @bit: the computed bit
98 */

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157 * The function disables all pinmux groups using a pin except the
158 * selected one. If @sel_group is -1 all groups are disabled, leaving
159 * the pin in GPIO mode.
160 */
161static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc,
162 unsigned int pin, int sel_group)
163{
164 struct meson_pmx_group *group;
193 struct meson_domain *domain;
194 int i, j;
195
196 for (i = 0; i < pc->data->num_groups; i++) {
197 group = &pc->data->groups[i];
198 if (group->is_gpio || i == sel_group)
199 continue;
200
201 for (j = 0; j < group->num_pins; j++) {
202 if (group->pins[j] == pin) {
203 /* We have found a group using the pin */
165 int i, j;
166
167 for (i = 0; i < pc->data->num_groups; i++) {
168 group = &pc->data->groups[i];
169 if (group->is_gpio || i == sel_group)
170 continue;
171
172 for (j = 0; j < group->num_pins; j++) {
173 if (group->pins[j] == pin) {
174 /* We have found a group using the pin */
204 domain = pc->domain;
205 regmap_update_bits(domain->reg_mux,
175 regmap_update_bits(pc->reg_mux,
206 group->reg * 4,
207 BIT(group->bit), 0);
208 }
209 }
210 }
211}
212
213static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
214 unsigned group_num)
215{
216 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
217 struct meson_pmx_func *func = &pc->data->funcs[func_num];
218 struct meson_pmx_group *group = &pc->data->groups[group_num];
176 group->reg * 4,
177 BIT(group->bit), 0);
178 }
179 }
180 }
181}
182
183static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
184 unsigned group_num)
185{
186 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
187 struct meson_pmx_func *func = &pc->data->funcs[func_num];
188 struct meson_pmx_group *group = &pc->data->groups[group_num];
219 struct meson_domain *domain = pc->domain;
220 int i, ret = 0;
221
222 dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
223 group->name);
224
225 /*
226 * Disable groups using the same pin.
227 * The selected group is not disabled to avoid glitches.
228 */
229 for (i = 0; i < group->num_pins; i++)
230 meson_pmx_disable_other_groups(pc, group->pins[i], group_num);
231
232 /* Function 0 (GPIO) doesn't need any additional setting */
233 if (func_num)
189 int i, ret = 0;
190
191 dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
192 group->name);
193
194 /*
195 * Disable groups using the same pin.
196 * The selected group is not disabled to avoid glitches.
197 */
198 for (i = 0; i < group->num_pins; i++)
199 meson_pmx_disable_other_groups(pc, group->pins[i], group_num);
200
201 /* Function 0 (GPIO) doesn't need any additional setting */
202 if (func_num)
234 ret = regmap_update_bits(domain->reg_mux, group->reg * 4,
203 ret = regmap_update_bits(pc->reg_mux, group->reg * 4,
235 BIT(group->bit), BIT(group->bit));
236
237 return ret;
238}
239
240static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev,
241 struct pinctrl_gpio_range *range,
242 unsigned offset)

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282 .get_function_groups = meson_pmx_get_groups,
283 .gpio_request_enable = meson_pmx_request_gpio,
284};
285
286static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
287 unsigned long *configs, unsigned num_configs)
288{
289 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
204 BIT(group->bit), BIT(group->bit));
205
206 return ret;
207}
208
209static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev,
210 struct pinctrl_gpio_range *range,
211 unsigned offset)

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251 .get_function_groups = meson_pmx_get_groups,
252 .gpio_request_enable = meson_pmx_request_gpio,
253};
254
255static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
256 unsigned long *configs, unsigned num_configs)
257{
258 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
290 struct meson_domain *domain;
291 struct meson_bank *bank;
292 enum pin_config_param param;
293 unsigned int reg, bit;
294 int i, ret;
295 u16 arg;
296
259 struct meson_bank *bank;
260 enum pin_config_param param;
261 unsigned int reg, bit;
262 int i, ret;
263 u16 arg;
264
297 ret = meson_get_domain_and_bank(pc, pin, &domain, &bank);
265 ret = meson_get_bank(pc, pin, &bank);
298 if (ret)
299 return ret;
300
301 for (i = 0; i < num_configs; i++) {
302 param = pinconf_to_config_param(configs[i]);
303 arg = pinconf_to_config_argument(configs[i]);
304
305 switch (param) {
306 case PIN_CONFIG_BIAS_DISABLE:
307 dev_dbg(pc->dev, "pin %u: disable bias\n", pin);
308
309 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
266 if (ret)
267 return ret;
268
269 for (i = 0; i < num_configs; i++) {
270 param = pinconf_to_config_param(configs[i]);
271 arg = pinconf_to_config_argument(configs[i]);
272
273 switch (param) {
274 case PIN_CONFIG_BIAS_DISABLE:
275 dev_dbg(pc->dev, "pin %u: disable bias\n", pin);
276
277 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
310 ret = regmap_update_bits(domain->reg_pull, reg,
278 ret = regmap_update_bits(pc->reg_pull, reg,
311 BIT(bit), 0);
312 if (ret)
313 return ret;
314 break;
315 case PIN_CONFIG_BIAS_PULL_UP:
316 dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin);
317
318 meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
319 &reg, &bit);
279 BIT(bit), 0);
280 if (ret)
281 return ret;
282 break;
283 case PIN_CONFIG_BIAS_PULL_UP:
284 dev_dbg(pc->dev, "pin %u: enable pull-up\n", pin);
285
286 meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
287 &reg, &bit);
320 ret = regmap_update_bits(domain->reg_pullen, reg,
288 ret = regmap_update_bits(pc->reg_pullen, reg,
321 BIT(bit), BIT(bit));
322 if (ret)
323 return ret;
324
325 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
289 BIT(bit), BIT(bit));
290 if (ret)
291 return ret;
292
293 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
326 ret = regmap_update_bits(domain->reg_pull, reg,
294 ret = regmap_update_bits(pc->reg_pull, reg,
327 BIT(bit), BIT(bit));
328 if (ret)
329 return ret;
330 break;
331 case PIN_CONFIG_BIAS_PULL_DOWN:
332 dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin);
333
334 meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
335 &reg, &bit);
295 BIT(bit), BIT(bit));
296 if (ret)
297 return ret;
298 break;
299 case PIN_CONFIG_BIAS_PULL_DOWN:
300 dev_dbg(pc->dev, "pin %u: enable pull-down\n", pin);
301
302 meson_calc_reg_and_bit(bank, pin, REG_PULLEN,
303 &reg, &bit);
336 ret = regmap_update_bits(domain->reg_pullen, reg,
304 ret = regmap_update_bits(pc->reg_pullen, reg,
337 BIT(bit), BIT(bit));
338 if (ret)
339 return ret;
340
341 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
305 BIT(bit), BIT(bit));
306 if (ret)
307 return ret;
308
309 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
342 ret = regmap_update_bits(domain->reg_pull, reg,
310 ret = regmap_update_bits(pc->reg_pull, reg,
343 BIT(bit), 0);
344 if (ret)
345 return ret;
346 break;
347 default:
348 return -ENOTSUPP;
349 }
350 }
351
352 return 0;
353}
354
355static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
356{
311 BIT(bit), 0);
312 if (ret)
313 return ret;
314 break;
315 default:
316 return -ENOTSUPP;
317 }
318 }
319
320 return 0;
321}
322
323static int meson_pinconf_get_pull(struct meson_pinctrl *pc, unsigned int pin)
324{
357 struct meson_domain *domain;
358 struct meson_bank *bank;
359 unsigned int reg, bit, val;
360 int ret, conf;
361
325 struct meson_bank *bank;
326 unsigned int reg, bit, val;
327 int ret, conf;
328
362 ret = meson_get_domain_and_bank(pc, pin, &domain, &bank);
329 ret = meson_get_bank(pc, pin, &bank);
363 if (ret)
364 return ret;
365
366 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg, &bit);
367
330 if (ret)
331 return ret;
332
333 meson_calc_reg_and_bit(bank, pin, REG_PULLEN, &reg, &bit);
334
368 ret = regmap_read(domain->reg_pullen, reg, &val);
335 ret = regmap_read(pc->reg_pullen, reg, &val);
369 if (ret)
370 return ret;
371
372 if (!(val & BIT(bit))) {
373 conf = PIN_CONFIG_BIAS_DISABLE;
374 } else {
375 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
376
336 if (ret)
337 return ret;
338
339 if (!(val & BIT(bit))) {
340 conf = PIN_CONFIG_BIAS_DISABLE;
341 } else {
342 meson_calc_reg_and_bit(bank, pin, REG_PULL, &reg, &bit);
343
377 ret = regmap_read(domain->reg_pull, reg, &val);
344 ret = regmap_read(pc->reg_pull, reg, &val);
378 if (ret)
379 return ret;
380
381 if (val & BIT(bit))
382 conf = PIN_CONFIG_BIAS_PULL_UP;
383 else
384 conf = PIN_CONFIG_BIAS_PULL_DOWN;
385 }

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447
448static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio)
449{
450 return pinctrl_request_gpio(chip->base + gpio);
451}
452
453static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio)
454{
345 if (ret)
346 return ret;
347
348 if (val & BIT(bit))
349 conf = PIN_CONFIG_BIAS_PULL_UP;
350 else
351 conf = PIN_CONFIG_BIAS_PULL_DOWN;
352 }

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414
415static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio)
416{
417 return pinctrl_request_gpio(chip->base + gpio);
418}
419
420static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio)
421{
455 struct meson_domain *domain = gpiochip_get_data(chip);
422 struct meson_pinctrl *pc = gpiochip_get_data(chip);
456
423
457 pinctrl_free_gpio(domain->data->pin_base + gpio);
424 pinctrl_free_gpio(pc->data->pin_base + gpio);
458}
459
460static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
461{
425}
426
427static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
428{
462 struct meson_domain *domain = gpiochip_get_data(chip);
429 struct meson_pinctrl *pc = gpiochip_get_data(chip);
463 unsigned int reg, bit, pin;
464 struct meson_bank *bank;
465 int ret;
466
430 unsigned int reg, bit, pin;
431 struct meson_bank *bank;
432 int ret;
433
467 pin = domain->data->pin_base + gpio;
468 ret = meson_get_bank(domain, pin, &bank);
434 pin = pc->data->pin_base + gpio;
435 ret = meson_get_bank(pc, pin, &bank);
469 if (ret)
470 return ret;
471
472 meson_calc_reg_and_bit(bank, pin, REG_DIR, &reg, &bit);
473
436 if (ret)
437 return ret;
438
439 meson_calc_reg_and_bit(bank, pin, REG_DIR, &reg, &bit);
440
474 return regmap_update_bits(domain->reg_gpio, reg, BIT(bit), BIT(bit));
441 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT(bit));
475}
476
477static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
478 int value)
479{
442}
443
444static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
445 int value)
446{
480 struct meson_domain *domain = gpiochip_get_data(chip);
447 struct meson_pinctrl *pc = gpiochip_get_data(chip);
481 unsigned int reg, bit, pin;
482 struct meson_bank *bank;
483 int ret;
484
448 unsigned int reg, bit, pin;
449 struct meson_bank *bank;
450 int ret;
451
485 pin = domain->data->pin_base + gpio;
486 ret = meson_get_bank(domain, pin, &bank);
452 pin = pc->data->pin_base + gpio;
453 ret = meson_get_bank(pc, pin, &bank);
487 if (ret)
488 return ret;
489
490 meson_calc_reg_and_bit(bank, pin, REG_DIR, &reg, &bit);
454 if (ret)
455 return ret;
456
457 meson_calc_reg_and_bit(bank, pin, REG_DIR, &reg, &bit);
491 ret = regmap_update_bits(domain->reg_gpio, reg, BIT(bit), 0);
458 ret = regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 0);
492 if (ret)
493 return ret;
494
495 meson_calc_reg_and_bit(bank, pin, REG_OUT, &reg, &bit);
459 if (ret)
460 return ret;
461
462 meson_calc_reg_and_bit(bank, pin, REG_OUT, &reg, &bit);
496 return regmap_update_bits(domain->reg_gpio, reg, BIT(bit),
463 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
497 value ? BIT(bit) : 0);
498}
499
500static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
501{
464 value ? BIT(bit) : 0);
465}
466
467static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
468{
502 struct meson_domain *domain = gpiochip_get_data(chip);
469 struct meson_pinctrl *pc = gpiochip_get_data(chip);
503 unsigned int reg, bit, pin;
504 struct meson_bank *bank;
505 int ret;
506
470 unsigned int reg, bit, pin;
471 struct meson_bank *bank;
472 int ret;
473
507 pin = domain->data->pin_base + gpio;
508 ret = meson_get_bank(domain, pin, &bank);
474 pin = pc->data->pin_base + gpio;
475 ret = meson_get_bank(pc, pin, &bank);
509 if (ret)
510 return;
511
512 meson_calc_reg_and_bit(bank, pin, REG_OUT, &reg, &bit);
476 if (ret)
477 return;
478
479 meson_calc_reg_and_bit(bank, pin, REG_OUT, &reg, &bit);
513 regmap_update_bits(domain->reg_gpio, reg, BIT(bit),
480 regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
514 value ? BIT(bit) : 0);
515}
516
517static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
518{
481 value ? BIT(bit) : 0);
482}
483
484static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
485{
519 struct meson_domain *domain = gpiochip_get_data(chip);
486 struct meson_pinctrl *pc = gpiochip_get_data(chip);
520 unsigned int reg, bit, val, pin;
521 struct meson_bank *bank;
522 int ret;
523
487 unsigned int reg, bit, val, pin;
488 struct meson_bank *bank;
489 int ret;
490
524 pin = domain->data->pin_base + gpio;
525 ret = meson_get_bank(domain, pin, &bank);
491 pin = pc->data->pin_base + gpio;
492 ret = meson_get_bank(pc, pin, &bank);
526 if (ret)
527 return ret;
528
529 meson_calc_reg_and_bit(bank, pin, REG_IN, &reg, &bit);
493 if (ret)
494 return ret;
495
496 meson_calc_reg_and_bit(bank, pin, REG_IN, &reg, &bit);
530 regmap_read(domain->reg_gpio, reg, &val);
497 regmap_read(pc->reg_gpio, reg, &val);
531
532 return !!(val & BIT(bit));
533}
534
535static const struct of_device_id meson_pinctrl_dt_match[] = {
536 {
537 .compatible = "amlogic,meson8-cbus-pinctrl",
538 .data = &meson8_cbus_pinctrl_data,

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557 .compatible = "amlogic,meson-gxbb-aobus-pinctrl",
558 .data = &meson_gxbb_aobus_pinctrl_data,
559 },
560 { },
561};
562
563static int meson_gpiolib_register(struct meson_pinctrl *pc)
564{
498
499 return !!(val & BIT(bit));
500}
501
502static const struct of_device_id meson_pinctrl_dt_match[] = {
503 {
504 .compatible = "amlogic,meson8-cbus-pinctrl",
505 .data = &meson8_cbus_pinctrl_data,

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524 .compatible = "amlogic,meson-gxbb-aobus-pinctrl",
525 .data = &meson_gxbb_aobus_pinctrl_data,
526 },
527 { },
528};
529
530static int meson_gpiolib_register(struct meson_pinctrl *pc)
531{
565 struct meson_domain *domain;
566 int ret;
567
532 int ret;
533
568 domain = pc->domain;
534 pc->chip.label = pc->data->name;
535 pc->chip.parent = pc->dev;
536 pc->chip.request = meson_gpio_request;
537 pc->chip.free = meson_gpio_free;
538 pc->chip.direction_input = meson_gpio_direction_input;
539 pc->chip.direction_output = meson_gpio_direction_output;
540 pc->chip.get = meson_gpio_get;
541 pc->chip.set = meson_gpio_set;
542 pc->chip.base = pc->data->pin_base;
543 pc->chip.ngpio = pc->data->num_pins;
544 pc->chip.can_sleep = false;
545 pc->chip.of_node = pc->of_node;
546 pc->chip.of_gpio_n_cells = 2;
569
547
570 domain->chip.label = domain->data->name;
571 domain->chip.parent = pc->dev;
572 domain->chip.request = meson_gpio_request;
573 domain->chip.free = meson_gpio_free;
574 domain->chip.direction_input = meson_gpio_direction_input;
575 domain->chip.direction_output = meson_gpio_direction_output;
576 domain->chip.get = meson_gpio_get;
577 domain->chip.set = meson_gpio_set;
578 domain->chip.base = domain->data->pin_base;
579 domain->chip.ngpio = domain->data->num_pins;
580 domain->chip.can_sleep = false;
581 domain->chip.of_node = domain->of_node;
582 domain->chip.of_gpio_n_cells = 2;
583
584 ret = gpiochip_add_data(&domain->chip, domain);
548 ret = gpiochip_add_data(&pc->chip, pc);
585 if (ret) {
586 dev_err(pc->dev, "can't add gpio chip %s\n",
549 if (ret) {
550 dev_err(pc->dev, "can't add gpio chip %s\n",
587 domain->data->name);
551 pc->data->name);
588 goto fail;
589 }
590
552 goto fail;
553 }
554
591 ret = gpiochip_add_pin_range(&domain->chip, dev_name(pc->dev),
592 0, domain->data->pin_base,
593 domain->chip.ngpio);
555 ret = gpiochip_add_pin_range(&pc->chip, dev_name(pc->dev),
556 0, pc->data->pin_base,
557 pc->chip.ngpio);
594 if (ret) {
595 dev_err(pc->dev, "can't add pin range\n");
596 goto fail;
597 }
598
599 return 0;
600fail:
558 if (ret) {
559 dev_err(pc->dev, "can't add pin range\n");
560 goto fail;
561 }
562
563 return 0;
564fail:
601 gpiochip_remove(&pc->domain->chip);
565 gpiochip_remove(&pc->chip);
602
603 return ret;
604}
605
606static struct regmap_config meson_regmap_config = {
607 .reg_bits = 32,
608 .val_bits = 32,
609 .reg_stride = 4,

--- 22 unchanged lines hidden (view full) ---

632 return ERR_PTR(-ENOMEM);
633
634 return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config);
635}
636
637static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
638 struct device_node *node)
639{
566
567 return ret;
568}
569
570static struct regmap_config meson_regmap_config = {
571 .reg_bits = 32,
572 .val_bits = 32,
573 .reg_stride = 4,

--- 22 unchanged lines hidden (view full) ---

596 return ERR_PTR(-ENOMEM);
597
598 return devm_regmap_init_mmio(pc->dev, base, &meson_regmap_config);
599}
600
601static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
602 struct device_node *node)
603{
640 struct device_node *np;
641 struct meson_domain *domain;
642 int num_domains = 0;
604 struct device_node *np, *gpio_np = NULL;
643
644 for_each_child_of_node(node, np) {
645 if (!of_find_property(np, "gpio-controller", NULL))
646 continue;
605
606 for_each_child_of_node(node, np) {
607 if (!of_find_property(np, "gpio-controller", NULL))
608 continue;
647 num_domains++;
609 if (gpio_np) {
610 dev_err(pc->dev, "multiple gpio nodes\n");
611 return -EINVAL;
612 }
613 gpio_np = np;
648 }
649
614 }
615
650 if (num_domains != 1) {
651 dev_err(pc->dev, "wrong number of subnodes\n");
616 if (!gpio_np) {
617 dev_err(pc->dev, "no gpio node found\n");
652 return -EINVAL;
653 }
654
618 return -EINVAL;
619 }
620
655 pc->domain = devm_kzalloc(pc->dev, sizeof(struct meson_domain), GFP_KERNEL);
656 if (!pc->domain)
657 return -ENOMEM;
621 pc->of_node = gpio_np;
658
622
659 domain = pc->domain;
660 domain->data = pc->data->domain_data;
623 pc->reg_mux = meson_map_resource(pc, gpio_np, "mux");
624 if (IS_ERR(pc->reg_mux)) {
625 dev_err(pc->dev, "mux registers not found\n");
626 return PTR_ERR(pc->reg_mux);
627 }
661
628
662 for_each_child_of_node(node, np) {
663 if (!of_find_property(np, "gpio-controller", NULL))
664 continue;
629 pc->reg_pull = meson_map_resource(pc, gpio_np, "pull");
630 if (IS_ERR(pc->reg_pull)) {
631 dev_err(pc->dev, "pull registers not found\n");
632 return PTR_ERR(pc->reg_pull);
633 }
665
634
666 domain->of_node = np;
635 pc->reg_pullen = meson_map_resource(pc, gpio_np, "pull-enable");
636 /* Use pull region if pull-enable one is not present */
637 if (IS_ERR(pc->reg_pullen))
638 pc->reg_pullen = pc->reg_pull;
667
639
668 domain->reg_mux = meson_map_resource(pc, np, "mux");
669 if (IS_ERR(domain->reg_mux)) {
670 dev_err(pc->dev, "mux registers not found\n");
671 return PTR_ERR(domain->reg_mux);
672 }
673
674 domain->reg_pull = meson_map_resource(pc, np, "pull");
675 if (IS_ERR(domain->reg_pull)) {
676 dev_err(pc->dev, "pull registers not found\n");
677 return PTR_ERR(domain->reg_pull);
678 }
679
680 domain->reg_pullen = meson_map_resource(pc, np, "pull-enable");
681 /* Use pull region if pull-enable one is not present */
682 if (IS_ERR(domain->reg_pullen))
683 domain->reg_pullen = domain->reg_pull;
684
685 domain->reg_gpio = meson_map_resource(pc, np, "gpio");
686 if (IS_ERR(domain->reg_gpio)) {
687 dev_err(pc->dev, "gpio registers not found\n");
688 return PTR_ERR(domain->reg_gpio);
689 }
690
691 break;
640 pc->reg_gpio = meson_map_resource(pc, gpio_np, "gpio");
641 if (IS_ERR(pc->reg_gpio)) {
642 dev_err(pc->dev, "gpio registers not found\n");
643 return PTR_ERR(pc->reg_gpio);
692 }
693
694 return 0;
695}
696
697static int meson_pinctrl_probe(struct platform_device *pdev)
698{
699 const struct of_device_id *match;

--- 22 unchanged lines hidden (view full) ---

722 pc->desc.npins = pc->data->num_pins;
723
724 pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc);
725 if (IS_ERR(pc->pcdev)) {
726 dev_err(pc->dev, "can't register pinctrl device");
727 return PTR_ERR(pc->pcdev);
728 }
729
644 }
645
646 return 0;
647}
648
649static int meson_pinctrl_probe(struct platform_device *pdev)
650{
651 const struct of_device_id *match;

--- 22 unchanged lines hidden (view full) ---

674 pc->desc.npins = pc->data->num_pins;
675
676 pc->pcdev = devm_pinctrl_register(pc->dev, &pc->desc, pc);
677 if (IS_ERR(pc->pcdev)) {
678 dev_err(pc->dev, "can't register pinctrl device");
679 return PTR_ERR(pc->pcdev);
680 }
681
730 return meson_gpiolib_register(pc);
682 ret = meson_gpiolib_register(pc);
683 if (ret) {
684 pinctrl_unregister(pc->pcdev);
685 return ret;
686 }
687
688 return 0;
731}
732
733static struct platform_driver meson_pinctrl_driver = {
734 .probe = meson_pinctrl_probe,
735 .driver = {
736 .name = "meson-pinctrl",
737 .of_match_table = meson_pinctrl_dt_match,
738 },
739};
740builtin_platform_driver(meson_pinctrl_driver);
689}
690
691static struct platform_driver meson_pinctrl_driver = {
692 .probe = meson_pinctrl_probe,
693 .driver = {
694 .name = "meson-pinctrl",
695 .of_match_table = meson_pinctrl_dt_match,
696 },
697};
698builtin_platform_driver(meson_pinctrl_driver);