pinctrl-bcm2835.c (7b88f1a4896ca7e8a490218af69077ade1ae43e4) pinctrl-bcm2835.c (85ae9e512f437cd09bf61564bdba29ab88bab3e3)
1/*
2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
3 *
4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
5 *
6 * This driver is inspired by:
7 * pinctrl-nomadik.c, please see original file for copyright information
8 * pinctrl-tegra.c, please see original file for copyright information

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19 */
20
21#include <linux/bitmap.h>
22#include <linux/bug.h>
23#include <linux/delay.h>
24#include <linux/device.h>
25#include <linux/err.h>
26#include <linux/gpio/driver.h>
1/*
2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
3 *
4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
5 *
6 * This driver is inspired by:
7 * pinctrl-nomadik.c, please see original file for copyright information
8 * pinctrl-tegra.c, please see original file for copyright information

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19 */
20
21#include <linux/bitmap.h>
22#include <linux/bug.h>
23#include <linux/delay.h>
24#include <linux/device.h>
25#include <linux/err.h>
26#include <linux/gpio/driver.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/irq.h>
30#include <linux/irqdesc.h>
27#include <linux/io.h>
28#include <linux/irq.h>
29#include <linux/irqdesc.h>
31#include <linux/irqdomain.h>
32#include <linux/module.h>
33#include <linux/of_address.h>
34#include <linux/of.h>
35#include <linux/of_irq.h>
36#include <linux/pinctrl/consumer.h>
37#include <linux/pinctrl/machine.h>
38#include <linux/pinctrl/pinconf.h>
39#include <linux/pinctrl/pinctrl.h>
40#include <linux/pinctrl/pinmux.h>
41#include <linux/platform_device.h>
42#include <linux/seq_file.h>
43#include <linux/slab.h>
44#include <linux/spinlock.h>
45#include <linux/types.h>
46
47#define MODULE_NAME "pinctrl-bcm2835"
48#define BCM2835_NUM_GPIOS 54
49#define BCM2835_NUM_BANKS 2
30#include <linux/module.h>
31#include <linux/of_address.h>
32#include <linux/of.h>
33#include <linux/of_irq.h>
34#include <linux/pinctrl/consumer.h>
35#include <linux/pinctrl/machine.h>
36#include <linux/pinctrl/pinconf.h>
37#include <linux/pinctrl/pinctrl.h>
38#include <linux/pinctrl/pinmux.h>
39#include <linux/platform_device.h>
40#include <linux/seq_file.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/types.h>
44
45#define MODULE_NAME "pinctrl-bcm2835"
46#define BCM2835_NUM_GPIOS 54
47#define BCM2835_NUM_BANKS 2
48#define BCM2835_NUM_IRQS 3
50
51#define BCM2835_PIN_BITMAP_SZ \
52 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
53
54/* GPIO register offsets */
55#define GPFSEL0 0x0 /* Function Select */
56#define GPSET0 0x1c /* Pin Output Set */
57#define GPCLR0 0x28 /* Pin Output Clear */

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71#define GPIO_REG_OFFSET(p) ((p) / 32)
72#define GPIO_REG_SHIFT(p) ((p) % 32)
73
74enum bcm2835_pinconf_param {
75 /* argument: bcm2835_pinconf_pull */
76 BCM2835_PINCONF_PARAM_PULL,
77};
78
49
50#define BCM2835_PIN_BITMAP_SZ \
51 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
52
53/* GPIO register offsets */
54#define GPFSEL0 0x0 /* Function Select */
55#define GPSET0 0x1c /* Pin Output Set */
56#define GPCLR0 0x28 /* Pin Output Clear */

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70#define GPIO_REG_OFFSET(p) ((p) / 32)
71#define GPIO_REG_SHIFT(p) ((p) % 32)
72
73enum bcm2835_pinconf_param {
74 /* argument: bcm2835_pinconf_pull */
75 BCM2835_PINCONF_PARAM_PULL,
76};
77
78enum bcm2835_pinconf_pull {
79 BCM2835_PINCONFIG_PULL_NONE,
80 BCM2835_PINCONFIG_PULL_DOWN,
81 BCM2835_PINCONFIG_PULL_UP,
82};
83
79#define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
80#define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
81#define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
82
84#define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
85#define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
86#define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
87
83struct bcm2835_gpio_irqdata {
84 struct bcm2835_pinctrl *pc;
85 int bank;
86};
87
88struct bcm2835_pinctrl {
89 struct device *dev;
90 void __iomem *base;
88struct bcm2835_pinctrl {
89 struct device *dev;
90 void __iomem *base;
91 int irq[BCM2835_NUM_BANKS];
91 int irq[BCM2835_NUM_IRQS];
92
93 /* note: locking assumes each bank will have its own unsigned long */
94 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
95 unsigned int irq_type[BCM2835_NUM_GPIOS];
96
97 struct pinctrl_dev *pctl_dev;
92
93 /* note: locking assumes each bank will have its own unsigned long */
94 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
95 unsigned int irq_type[BCM2835_NUM_GPIOS];
96
97 struct pinctrl_dev *pctl_dev;
98 struct irq_domain *irq_domain;
99 struct gpio_chip gpio_chip;
100 struct pinctrl_gpio_range gpio_range;
101
98 struct gpio_chip gpio_chip;
99 struct pinctrl_gpio_range gpio_range;
100
102 struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS];
101 int irq_group[BCM2835_NUM_IRQS];
103 spinlock_t irq_lock[BCM2835_NUM_BANKS];
104};
105
102 spinlock_t irq_lock[BCM2835_NUM_BANKS];
103};
104
106static struct lock_class_key gpio_lock_class;
107
108/* pins are just named GPIO0..GPIO53 */
109#define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
110static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
111 BCM2835_GPIO_PIN(0),
112 BCM2835_GPIO_PIN(1),
113 BCM2835_GPIO_PIN(2),
114 BCM2835_GPIO_PIN(3),
115 BCM2835_GPIO_PIN(4),

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357
358static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
359 unsigned offset, int value)
360{
361 bcm2835_gpio_set(chip, offset, value);
362 return pinctrl_gpio_direction_output(chip->base + offset);
363}
364
105/* pins are just named GPIO0..GPIO53 */
106#define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
107static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
108 BCM2835_GPIO_PIN(0),
109 BCM2835_GPIO_PIN(1),
110 BCM2835_GPIO_PIN(2),
111 BCM2835_GPIO_PIN(3),
112 BCM2835_GPIO_PIN(4),

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354
355static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
356 unsigned offset, int value)
357{
358 bcm2835_gpio_set(chip, offset, value);
359 return pinctrl_gpio_direction_output(chip->base + offset);
360}
361
365static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
366{
367 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
368
369 return irq_linear_revmap(pc->irq_domain, offset);
370}
371
372static struct gpio_chip bcm2835_gpio_chip = {
373 .label = MODULE_NAME,
374 .owner = THIS_MODULE,
375 .request = gpiochip_generic_request,
376 .free = gpiochip_generic_free,
377 .direction_input = bcm2835_gpio_direction_input,
378 .direction_output = bcm2835_gpio_direction_output,
379 .get_direction = bcm2835_gpio_get_direction,
380 .get = bcm2835_gpio_get,
381 .set = bcm2835_gpio_set,
362static struct gpio_chip bcm2835_gpio_chip = {
363 .label = MODULE_NAME,
364 .owner = THIS_MODULE,
365 .request = gpiochip_generic_request,
366 .free = gpiochip_generic_free,
367 .direction_input = bcm2835_gpio_direction_input,
368 .direction_output = bcm2835_gpio_direction_output,
369 .get_direction = bcm2835_gpio_get_direction,
370 .get = bcm2835_gpio_get,
371 .set = bcm2835_gpio_set,
382 .to_irq = bcm2835_gpio_to_irq,
383 .base = -1,
384 .ngpio = BCM2835_NUM_GPIOS,
385 .can_sleep = false,
386};
387
372 .base = -1,
373 .ngpio = BCM2835_NUM_GPIOS,
374 .can_sleep = false,
375};
376
388static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
377static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
378 unsigned int bank, u32 mask)
389{
379{
390 struct bcm2835_gpio_irqdata *irqdata = dev_id;
391 struct bcm2835_pinctrl *pc = irqdata->pc;
392 int bank = irqdata->bank;
393 unsigned long events;
394 unsigned offset;
395 unsigned gpio;
396 unsigned int type;
397
398 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
380 unsigned long events;
381 unsigned offset;
382 unsigned gpio;
383 unsigned int type;
384
385 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
386 events &= mask;
399 events &= pc->enabled_irq_map[bank];
400 for_each_set_bit(offset, &events, 32) {
401 gpio = (32 * bank) + offset;
387 events &= pc->enabled_irq_map[bank];
388 for_each_set_bit(offset, &events, 32) {
389 gpio = (32 * bank) + offset;
390 /* FIXME: no clue why the code looks up the type here */
402 type = pc->irq_type[gpio];
403
391 type = pc->irq_type[gpio];
392
404 generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio));
393 generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irqdomain,
394 gpio));
405 }
395 }
406 return events ? IRQ_HANDLED : IRQ_NONE;
407}
408
396}
397
398static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
399{
400 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
401 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
402 struct irq_chip *host_chip = irq_desc_get_chip(desc);
403 int irq = irq_desc_get_irq(desc);
404 int group;
405 int i;
406
407 for (i = 0; i < ARRAY_SIZE(pc->irq); i++) {
408 if (pc->irq[i] == irq) {
409 group = pc->irq_group[i];
410 break;
411 }
412 }
413 /* This should not happen, every IRQ has a bank */
414 if (i == ARRAY_SIZE(pc->irq))
415 BUG();
416
417 chained_irq_enter(host_chip, desc);
418
419 switch (group) {
420 case 0: /* IRQ0 covers GPIOs 0-27 */
421 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
422 break;
423 case 1: /* IRQ1 covers GPIOs 28-45 */
424 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
425 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
426 break;
427 case 2: /* IRQ2 covers GPIOs 46-53 */
428 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
429 break;
430 }
431
432 chained_irq_exit(host_chip, desc);
433}
434
409static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
410 unsigned reg, unsigned offset, bool enable)
411{
412 u32 value;
413 reg += GPIO_REG_OFFSET(offset) * 4;
414 value = bcm2835_gpio_rd(pc, reg);
415 if (enable)
416 value |= BIT(GPIO_REG_SHIFT(offset));

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444 case IRQ_TYPE_LEVEL_LOW:
445 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
446 break;
447 }
448}
449
450static void bcm2835_gpio_irq_enable(struct irq_data *data)
451{
435static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
436 unsigned reg, unsigned offset, bool enable)
437{
438 u32 value;
439 reg += GPIO_REG_OFFSET(offset) * 4;
440 value = bcm2835_gpio_rd(pc, reg);
441 if (enable)
442 value |= BIT(GPIO_REG_SHIFT(offset));

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470 case IRQ_TYPE_LEVEL_LOW:
471 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
472 break;
473 }
474}
475
476static void bcm2835_gpio_irq_enable(struct irq_data *data)
477{
452 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
478 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
479 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
453 unsigned gpio = irqd_to_hwirq(data);
454 unsigned offset = GPIO_REG_SHIFT(gpio);
455 unsigned bank = GPIO_REG_OFFSET(gpio);
456 unsigned long flags;
457
458 spin_lock_irqsave(&pc->irq_lock[bank], flags);
459 set_bit(offset, &pc->enabled_irq_map[bank]);
460 bcm2835_gpio_irq_config(pc, gpio, true);
461 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
462}
463
464static void bcm2835_gpio_irq_disable(struct irq_data *data)
465{
480 unsigned gpio = irqd_to_hwirq(data);
481 unsigned offset = GPIO_REG_SHIFT(gpio);
482 unsigned bank = GPIO_REG_OFFSET(gpio);
483 unsigned long flags;
484
485 spin_lock_irqsave(&pc->irq_lock[bank], flags);
486 set_bit(offset, &pc->enabled_irq_map[bank]);
487 bcm2835_gpio_irq_config(pc, gpio, true);
488 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
489}
490
491static void bcm2835_gpio_irq_disable(struct irq_data *data)
492{
466 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
493 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
494 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
467 unsigned gpio = irqd_to_hwirq(data);
468 unsigned offset = GPIO_REG_SHIFT(gpio);
469 unsigned bank = GPIO_REG_OFFSET(gpio);
470 unsigned long flags;
471
472 spin_lock_irqsave(&pc->irq_lock[bank], flags);
473 bcm2835_gpio_irq_config(pc, gpio, false);
474 /* Clear events that were latched prior to clearing event sources */

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564 default:
565 return -EINVAL;
566 }
567 return 0;
568}
569
570static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
571{
495 unsigned gpio = irqd_to_hwirq(data);
496 unsigned offset = GPIO_REG_SHIFT(gpio);
497 unsigned bank = GPIO_REG_OFFSET(gpio);
498 unsigned long flags;
499
500 spin_lock_irqsave(&pc->irq_lock[bank], flags);
501 bcm2835_gpio_irq_config(pc, gpio, false);
502 /* Clear events that were latched prior to clearing event sources */

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592 default:
593 return -EINVAL;
594 }
595 return 0;
596}
597
598static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
599{
572 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
600 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
601 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
573 unsigned gpio = irqd_to_hwirq(data);
574 unsigned offset = GPIO_REG_SHIFT(gpio);
575 unsigned bank = GPIO_REG_OFFSET(gpio);
576 unsigned long flags;
577 int ret;
578
579 spin_lock_irqsave(&pc->irq_lock[bank], flags);
580

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590
591 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
592
593 return ret;
594}
595
596static void bcm2835_gpio_irq_ack(struct irq_data *data)
597{
602 unsigned gpio = irqd_to_hwirq(data);
603 unsigned offset = GPIO_REG_SHIFT(gpio);
604 unsigned bank = GPIO_REG_OFFSET(gpio);
605 unsigned long flags;
606 int ret;
607
608 spin_lock_irqsave(&pc->irq_lock[bank], flags);
609

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619
620 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
621
622 return ret;
623}
624
625static void bcm2835_gpio_irq_ack(struct irq_data *data)
626{
598 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
627 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
628 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
599 unsigned gpio = irqd_to_hwirq(data);
600
601 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
602}
603
604static struct irq_chip bcm2835_gpio_irq_chip = {
605 .name = MODULE_NAME,
606 .irq_enable = bcm2835_gpio_irq_enable,

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633 return 0;
634}
635
636static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
637 struct seq_file *s,
638 unsigned offset)
639{
640 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
629 unsigned gpio = irqd_to_hwirq(data);
630
631 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
632}
633
634static struct irq_chip bcm2835_gpio_irq_chip = {
635 .name = MODULE_NAME,
636 .irq_enable = bcm2835_gpio_irq_enable,

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663 return 0;
664}
665
666static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
667 struct seq_file *s,
668 unsigned offset)
669{
670 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
671 struct gpio_chip *chip = &pc->gpio_chip;
641 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
642 const char *fname = bcm2835_functions[fsel];
643 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
672 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
673 const char *fname = bcm2835_functions[fsel];
674 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
644 int irq = irq_find_mapping(pc->irq_domain, offset);
675 int irq = irq_find_mapping(chip->irqdomain, offset);
645
646 seq_printf(s, "function %s in %s; irq %d (%s)",
647 fname, value ? "hi" : "lo",
648 irq, irq_type_names[pc->irq_type[offset]]);
649}
650
651static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
652 struct pinctrl_map *maps, unsigned num_maps)

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810 .get_groups_count = bcm2835_pctl_get_groups_count,
811 .get_group_name = bcm2835_pctl_get_group_name,
812 .get_group_pins = bcm2835_pctl_get_group_pins,
813 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
814 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
815 .dt_free_map = bcm2835_pctl_dt_free_map,
816};
817
676
677 seq_printf(s, "function %s in %s; irq %d (%s)",
678 fname, value ? "hi" : "lo",
679 irq, irq_type_names[pc->irq_type[offset]]);
680}
681
682static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
683 struct pinctrl_map *maps, unsigned num_maps)

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841 .get_groups_count = bcm2835_pctl_get_groups_count,
842 .get_group_name = bcm2835_pctl_get_group_name,
843 .get_group_pins = bcm2835_pctl_get_group_pins,
844 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
845 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
846 .dt_free_map = bcm2835_pctl_dt_free_map,
847};
848
849static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
850 unsigned offset)
851{
852 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
853
854 /* disable by setting to GPIO_IN */
855 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
856 return 0;
857}
858
818static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
819{
820 return BCM2835_FSEL_COUNT;
821}
822
823static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
824 unsigned selector)
825{

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869 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
870
871 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
872
873 return 0;
874}
875
876static const struct pinmux_ops bcm2835_pmx_ops = {
859static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
860{
861 return BCM2835_FSEL_COUNT;
862}
863
864static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
865 unsigned selector)
866{

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910 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
911
912 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
913
914 return 0;
915}
916
917static const struct pinmux_ops bcm2835_pmx_ops = {
918 .free = bcm2835_pmx_free,
877 .get_functions_count = bcm2835_pmx_get_functions_count,
878 .get_function_name = bcm2835_pmx_get_function_name,
879 .get_function_groups = bcm2835_pmx_get_function_groups,
880 .set_mux = bcm2835_pmx_set,
881 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
882 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
883};
884

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906 if (param != BCM2835_PINCONF_PARAM_PULL)
907 return -EINVAL;
908
909 off = GPIO_REG_OFFSET(pin);
910 bit = GPIO_REG_SHIFT(pin);
911
912 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
913 /*
919 .get_functions_count = bcm2835_pmx_get_functions_count,
920 .get_function_name = bcm2835_pmx_get_function_name,
921 .get_function_groups = bcm2835_pmx_get_function_groups,
922 .set_mux = bcm2835_pmx_set,
923 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
924 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
925};
926

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948 if (param != BCM2835_PINCONF_PARAM_PULL)
949 return -EINVAL;
950
951 off = GPIO_REG_OFFSET(pin);
952 bit = GPIO_REG_SHIFT(pin);
953
954 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
955 /*
914 * Docs say to wait 150 cycles, but not of what. We assume a
915 * 1 MHz clock here, which is pretty slow...
956 * BCM2835 datasheet say to wait 150 cycles, but not of what.
957 * But the VideoCore firmware delay for this operation
958 * based nearly on the same amount of VPU cycles and this clock
959 * runs at 250 MHz.
916 */
960 */
917 udelay(150);
961 udelay(1);
918 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
962 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
919 udelay(150);
963 udelay(1);
920 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
921 } /* for each config */
922
923 return 0;
924}
925
926static const struct pinconf_ops bcm2835_pinconf_ops = {
927 .pin_config_get = bcm2835_pinconf_get,

--- 41 unchanged lines hidden (view full) ---

969 pc->base = devm_ioremap_resource(dev, &iomem);
970 if (IS_ERR(pc->base))
971 return PTR_ERR(pc->base);
972
973 pc->gpio_chip = bcm2835_gpio_chip;
974 pc->gpio_chip.parent = dev;
975 pc->gpio_chip.of_node = np;
976
964 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
965 } /* for each config */
966
967 return 0;
968}
969
970static const struct pinconf_ops bcm2835_pinconf_ops = {
971 .pin_config_get = bcm2835_pinconf_get,

--- 41 unchanged lines hidden (view full) ---

1013 pc->base = devm_ioremap_resource(dev, &iomem);
1014 if (IS_ERR(pc->base))
1015 return PTR_ERR(pc->base);
1016
1017 pc->gpio_chip = bcm2835_gpio_chip;
1018 pc->gpio_chip.parent = dev;
1019 pc->gpio_chip.of_node = np;
1020
977 pc->irq_domain = irq_domain_add_linear(np, BCM2835_NUM_GPIOS,
978 &irq_domain_simple_ops, NULL);
979 if (!pc->irq_domain) {
980 dev_err(dev, "could not create IRQ domain\n");
981 return -ENOMEM;
982 }
983
984 for (i = 0; i < BCM2835_NUM_GPIOS; i++) {
985 int irq = irq_create_mapping(pc->irq_domain, i);
986 irq_set_lockdep_class(irq, &gpio_lock_class);
987 irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip,
988 handle_level_irq);
989 irq_set_chip_data(irq, pc);
990 }
991
992 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
993 unsigned long events;
994 unsigned offset;
1021 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1022 unsigned long events;
1023 unsigned offset;
995 int len;
996 char *name;
997
998 /* clear event detection flags */
999 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1000 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1001 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1002 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1003 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1004 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1005
1006 /* clear all the events */
1007 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1008 for_each_set_bit(offset, &events, 32)
1009 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1010
1024
1025 /* clear event detection flags */
1026 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1027 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1028 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1029 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1030 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1031 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1032
1033 /* clear all the events */
1034 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1035 for_each_set_bit(offset, &events, 32)
1036 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1037
1011 pc->irq[i] = irq_of_parse_and_map(np, i);
1012 pc->irq_data[i].pc = pc;
1013 pc->irq_data[i].bank = i;
1014 spin_lock_init(&pc->irq_lock[i]);
1038 spin_lock_init(&pc->irq_lock[i]);
1015
1016 len = strlen(dev_name(pc->dev)) + 16;
1017 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1018 if (!name)
1019 return -ENOMEM;
1020 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1021
1022 err = devm_request_irq(dev, pc->irq[i],
1023 bcm2835_gpio_irq_handler, IRQF_SHARED,
1024 name, &pc->irq_data[i]);
1025 if (err) {
1026 dev_err(dev, "unable to request IRQ %d\n", pc->irq[i]);
1027 return err;
1028 }
1029 }
1030
1031 err = gpiochip_add_data(&pc->gpio_chip, pc);
1032 if (err) {
1033 dev_err(dev, "could not add GPIO chip\n");
1034 return err;
1035 }
1036
1039 }
1040
1041 err = gpiochip_add_data(&pc->gpio_chip, pc);
1042 if (err) {
1043 dev_err(dev, "could not add GPIO chip\n");
1044 return err;
1045 }
1046
1047 err = gpiochip_irqchip_add(&pc->gpio_chip, &bcm2835_gpio_irq_chip,
1048 0, handle_level_irq, IRQ_TYPE_NONE);
1049 if (err) {
1050 dev_info(dev, "could not add irqchip\n");
1051 return err;
1052 }
1053
1054 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1055 pc->irq[i] = irq_of_parse_and_map(np, i);
1056 pc->irq_group[i] = i;
1057 /*
1058 * Use the same handler for all groups: this is necessary
1059 * since we use one gpiochip to cover all lines - the
1060 * irq handler then needs to figure out which group and
1061 * bank that was firing the IRQ and look up the per-group
1062 * and bank data.
1063 */
1064 gpiochip_set_chained_irqchip(&pc->gpio_chip,
1065 &bcm2835_gpio_irq_chip,
1066 pc->irq[i],
1067 bcm2835_gpio_irq_handler);
1068 }
1069
1037 pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
1038 if (IS_ERR(pc->pctl_dev)) {
1039 gpiochip_remove(&pc->gpio_chip);
1040 return PTR_ERR(pc->pctl_dev);
1041 }
1042
1043 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1044 pc->gpio_range.base = pc->gpio_chip.base;

--- 34 unchanged lines hidden --- 		1070 pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
1071 if (IS_ERR(pc->pctl_dev)) {
1072 gpiochip_remove(&pc->gpio_chip);
1073 return PTR_ERR(pc->pctl_dev);
1074 }
1075
1076 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1077 pc->gpio_range.base = pc->gpio_chip.base;

--- 34 unchanged lines hidden ---