pinctrl-s900.c (6b16f5d12202a23d875915349cc031c07fe1b3ec) pinctrl-s900.c (6c5d0736e9c09f00f5549f20390d6daae98a1bfd)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * OWL S900 Pinctrl driver
4 *
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Author: David Liu <liuwei@actions-semi.com>
7 *
8 * Copyright (c) 2018 Linaro Ltd.

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1816 [NAND1_CEB2] = PAD_INFO(NAND1_CEB2),
1817 [NAND1_CEB3] = PAD_INFO(NAND1_CEB3),
1818 [SGPIO0] = PAD_INFO(SGPIO0),
1819 [SGPIO1] = PAD_INFO(SGPIO1),
1820 [SGPIO2] = PAD_INFO_PULLCTL_ST(SGPIO2),
1821 [SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3)
1822};
1823
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * OWL S900 Pinctrl driver
4 *
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Author: David Liu <liuwei@actions-semi.com>
7 *
8 * Copyright (c) 2018 Linaro Ltd.

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1816 [NAND1_CEB2] = PAD_INFO(NAND1_CEB2),
1817 [NAND1_CEB3] = PAD_INFO(NAND1_CEB3),
1818 [SGPIO0] = PAD_INFO(SGPIO0),
1819 [SGPIO1] = PAD_INFO(SGPIO1),
1820 [SGPIO2] = PAD_INFO_PULLCTL_ST(SGPIO2),
1821 [SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3)
1822};
1823
1824#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat) \
1825 [OWL_GPIO_PORT_##port] = { \
1826 .offset = base, \
1827 .pins = count, \
1828 .outen = _outen, \
1829 .inen = _inen, \
1830 .dat = _dat, \
1824#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat, \
1825 _intc_ctl, _intc_pd, _intc_msk, _intc_type) \
1826 [OWL_GPIO_PORT_##port] = { \
1827 .offset = base, \
1828 .pins = count, \
1829 .outen = _outen, \
1830 .inen = _inen, \
1831 .dat = _dat, \
1832 .intc_ctl = _intc_ctl, \
1833 .intc_pd = _intc_pd, \
1834 .intc_msk = _intc_msk, \
1835 .intc_type = _intc_type, \
1831 }
1832
1833static const struct owl_gpio_port s900_gpio_ports[] = {
1836 }
1837
1838static const struct owl_gpio_port s900_gpio_ports[] = {
1834 OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8),
1835 OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8),
1836 OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8),
1837 OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8),
1838 OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8),
1839 OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8)
1839 OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240),
1840 OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C),
1841 OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238),
1842 OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234),
1843 OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230),
1844 OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178)
1840};
1841
1842static struct owl_pinctrl_soc_data s900_pinctrl_data = {
1843 .padinfo = s900_padinfo,
1844 .pins = (const struct pinctrl_pin_desc *)s900_pads,
1845 .npins = ARRAY_SIZE(s900_pads),
1846 .functions = s900_functions,
1847 .nfunctions = ARRAY_SIZE(s900_functions),

--- 41 unchanged lines hidden --- 		1845};
1846
1847static struct owl_pinctrl_soc_data s900_pinctrl_data = {
1848 .padinfo = s900_padinfo,
1849 .pins = (const struct pinctrl_pin_desc *)s900_pads,
1850 .npins = ARRAY_SIZE(s900_pads),
1851 .functions = s900_functions,
1852 .nfunctions = ARRAY_SIZE(s900_functions),

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