pinctrl-owl.h (6b16f5d12202a23d875915349cc031c07fe1b3ec) pinctrl-owl.h (6c5d0736e9c09f00f5549f20390d6daae98a1bfd)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * OWL SoC's Pinctrl definitions
4 *
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Author: David Liu <liuwei@actions-semi.com>
7 *
8 * Copyright (c) 2018 Linaro Ltd.

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24
25enum owl_pinconf_drv {
26 OWL_PINCONF_DRV_2MA,
27 OWL_PINCONF_DRV_4MA,
28 OWL_PINCONF_DRV_8MA,
29 OWL_PINCONF_DRV_12MA,
30};
31
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * OWL SoC's Pinctrl definitions
4 *
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Author: David Liu <liuwei@actions-semi.com>
7 *
8 * Copyright (c) 2018 Linaro Ltd.

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24
25enum owl_pinconf_drv {
26 OWL_PINCONF_DRV_2MA,
27 OWL_PINCONF_DRV_4MA,
28 OWL_PINCONF_DRV_8MA,
29 OWL_PINCONF_DRV_12MA,
30};
31
32/* GPIO CTRL Bit Definition */
33#define OWL_GPIO_CTLR_PENDING 0
34#define OWL_GPIO_CTLR_ENABLE 1
35#define OWL_GPIO_CTLR_SAMPLE_CLK_24M 2
36
37/* GPIO TYPE Bit Definition */
38#define OWL_GPIO_INT_LEVEL_HIGH 0
39#define OWL_GPIO_INT_LEVEL_LOW 1
40#define OWL_GPIO_INT_EDGE_RISING 2
41#define OWL_GPIO_INT_EDGE_FALLING 3
42#define OWL_GPIO_INT_MASK 3
43
32/**
33 * struct owl_pullctl - Actions pad pull control register
34 * @reg: offset to the pull control register
35 * @shift: shift value of the register
36 * @width: width of the register
37 */
38struct owl_pullctl {
39 int reg;

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116
117/**
118 * struct owl_gpio_port - Actions GPIO port info
119 * @offset: offset of the GPIO port.
120 * @pins: number of pins belongs to the GPIO port.
121 * @outen: offset of the output enable register.
122 * @inen: offset of the input enable register.
123 * @dat: offset of the data register.
44/**
45 * struct owl_pullctl - Actions pad pull control register
46 * @reg: offset to the pull control register
47 * @shift: shift value of the register
48 * @width: width of the register
49 */
50struct owl_pullctl {
51 int reg;

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128
129/**
130 * struct owl_gpio_port - Actions GPIO port info
131 * @offset: offset of the GPIO port.
132 * @pins: number of pins belongs to the GPIO port.
133 * @outen: offset of the output enable register.
134 * @inen: offset of the input enable register.
135 * @dat: offset of the data register.
136 * @intc_ctl: offset of the interrupt control register.
137 * @intc_pd: offset of the interrupt pending register.
138 * @intc_msk: offset of the interrupt mask register.
139 * @intc_type: offset of the interrupt type register.
124 */
125struct owl_gpio_port {
126 unsigned int offset;
127 unsigned int pins;
128 unsigned int outen;
129 unsigned int inen;
130 unsigned int dat;
140 */
141struct owl_gpio_port {
142 unsigned int offset;
143 unsigned int pins;
144 unsigned int outen;
145 unsigned int inen;
146 unsigned int dat;
147 unsigned int intc_ctl;
148 unsigned int intc_pd;
149 unsigned int intc_msk;
150 unsigned int intc_type;
131};
132
133/**
134 * struct owl_pinctrl_soc_data - Actions pin controller driver configuration
135 * @pins: array describing all pins of the pin controller.
136 * @npins: number of entries in @pins.
137 * @functions: array describing all mux functions of this SoC.
138 * @nfunction: number of entries in @functions.
139 * @groups: array describing all pin groups of this SoC.
140 * @ngroups: number of entries in @groups.
141 * @padinfo: array describing the pad info of this SoC.
142 * @ngpios: number of pingroups the driver should expose as GPIOs.
151};
152
153/**
154 * struct owl_pinctrl_soc_data - Actions pin controller driver configuration
155 * @pins: array describing all pins of the pin controller.
156 * @npins: number of entries in @pins.
157 * @functions: array describing all mux functions of this SoC.
158 * @nfunction: number of entries in @functions.
159 * @groups: array describing all pin groups of this SoC.
160 * @ngroups: number of entries in @groups.
161 * @padinfo: array describing the pad info of this SoC.
162 * @ngpios: number of pingroups the driver should expose as GPIOs.
143 * @port: array describing all GPIO ports of this SoC.
163 * @ports: array describing all GPIO ports of this SoC.
144 * @nports: number of GPIO ports in this SoC.
145 */
146struct owl_pinctrl_soc_data {
147 const struct pinctrl_pin_desc *pins;
148 unsigned int npins;
149 const struct owl_pinmux_func *functions;
150 unsigned int nfunctions;
151 const struct owl_pingroup *groups;
152 unsigned int ngroups;
153 const struct owl_padinfo *padinfo;
154 unsigned int ngpios;
155 const struct owl_gpio_port *ports;
156 unsigned int nports;
157};
158
159int owl_pinctrl_probe(struct platform_device *pdev,
160 struct owl_pinctrl_soc_data *soc_data);
161
162#endif /* __PINCTRL_OWL_H__ */
164 * @nports: number of GPIO ports in this SoC.
165 */
166struct owl_pinctrl_soc_data {
167 const struct pinctrl_pin_desc *pins;
168 unsigned int npins;
169 const struct owl_pinmux_func *functions;
170 unsigned int nfunctions;
171 const struct owl_pingroup *groups;
172 unsigned int ngroups;
173 const struct owl_padinfo *padinfo;
174 unsigned int ngpios;
175 const struct owl_gpio_port *ports;
176 unsigned int nports;
177};
178
179int owl_pinctrl_probe(struct platform_device *pdev,
180 struct owl_pinctrl_soc_data *soc_data);
181
182#endif /* __PINCTRL_OWL_H__ */