pinctrl-owl.c (c981c01164d5e47b98973f92d4680df4287275c2) pinctrl-owl.c (6c5d0736e9c09f00f5549f20390d6daae98a1bfd)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * OWL SoC's Pinctrl driver
4 *
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Author: David Liu <liuwei@actions-semi.com>
7 *
8 * Copyright (c) 2018 Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10 */
11
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/gpio/driver.h>
15#include <linux/io.h>
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * OWL SoC's Pinctrl driver
4 *
5 * Copyright (c) 2014 Actions Semi Inc.
6 * Author: David Liu <liuwei@actions-semi.com>
7 *
8 * Copyright (c) 2018 Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10 */
11
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/gpio/driver.h>
15#include <linux/io.h>
16#include <linux/irq.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/pinctrl/machine.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
22#include <linux/pinctrl/pinconf.h>
23#include <linux/pinctrl/pinconf-generic.h>

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40struct owl_pinctrl {
41 struct device *dev;
42 struct pinctrl_dev *pctrldev;
43 struct gpio_chip chip;
44 raw_spinlock_t lock;
45 struct clk *clk;
46 const struct owl_pinctrl_soc_data *soc;
47 void __iomem *base;
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/pinctrl/machine.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinmux.h>
23#include <linux/pinctrl/pinconf.h>
24#include <linux/pinctrl/pinconf-generic.h>

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41struct owl_pinctrl {
42 struct device *dev;
43 struct pinctrl_dev *pctrldev;
44 struct gpio_chip chip;
45 raw_spinlock_t lock;
46 struct clk *clk;
47 const struct owl_pinctrl_soc_data *soc;
48 void __iomem *base;
49 struct irq_chip irq_chip;
50 unsigned int num_irq;
51 unsigned int *irq;
48};
49
50static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
51{
52 u32 reg_val;
53
54 reg_val = readl_relaxed(base);
55

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328 unsigned long *configs,
329 unsigned int num_configs)
330{
331 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
332 const struct owl_padinfo *info;
333 unsigned long flags;
334 unsigned int param;
335 u32 reg, bit, width, arg;
52};
53
54static void owl_update_bits(void __iomem *base, u32 mask, u32 val)
55{
56 u32 reg_val;
57
58 reg_val = readl_relaxed(base);
59

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332 unsigned long *configs,
333 unsigned int num_configs)
334{
335 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
336 const struct owl_padinfo *info;
337 unsigned long flags;
338 unsigned int param;
339 u32 reg, bit, width, arg;
336 int ret = 0, i;
340 int ret, i;
337
338 info = &pctrl->soc->padinfo[pin];
339
340 for (i = 0; i < num_configs; i++) {
341 param = pinconf_to_config_param(configs[i]);
342 arg = pinconf_to_config_argument(configs[i]);
343
344 ret = owl_pad_pinconf_reg(info, param, &reg, &bit, &width);

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696 owl_gpio_update_reg(gpio_base + port->inen, offset, false);
697 owl_gpio_update_reg(gpio_base + port->outen, offset, true);
698 owl_gpio_update_reg(gpio_base + port->dat, offset, value);
699 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
700
701 return 0;
702}
703
341
342 info = &pctrl->soc->padinfo[pin];
343
344 for (i = 0; i < num_configs; i++) {
345 param = pinconf_to_config_param(configs[i]);
346 arg = pinconf_to_config_argument(configs[i]);
347
348 ret = owl_pad_pinconf_reg(info, param, &reg, &bit, &width);

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700 owl_gpio_update_reg(gpio_base + port->inen, offset, false);
701 owl_gpio_update_reg(gpio_base + port->outen, offset, true);
702 owl_gpio_update_reg(gpio_base + port->dat, offset, value);
703 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
704
705 return 0;
706}
707
708static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type)
709{
710 const struct owl_gpio_port *port;
711 void __iomem *gpio_base;
712 unsigned long flags;
713 unsigned int offset, value, irq_type = 0;
714
715 switch (type) {
716 case IRQ_TYPE_EDGE_BOTH:
717 /*
718 * Since the hardware doesn't support interrupts on both edges,
719 * emulate it in the software by setting the single edge
720 * interrupt and switching to the opposite edge while ACKing
721 * the interrupt
722 */
723 if (owl_gpio_get(&pctrl->chip, gpio))
724 irq_type = OWL_GPIO_INT_EDGE_FALLING;
725 else
726 irq_type = OWL_GPIO_INT_EDGE_RISING;
727 break;
728
729 case IRQ_TYPE_EDGE_RISING:
730 irq_type = OWL_GPIO_INT_EDGE_RISING;
731 break;
732
733 case IRQ_TYPE_EDGE_FALLING:
734 irq_type = OWL_GPIO_INT_EDGE_FALLING;
735 break;
736
737 case IRQ_TYPE_LEVEL_HIGH:
738 irq_type = OWL_GPIO_INT_LEVEL_HIGH;
739 break;
740
741 case IRQ_TYPE_LEVEL_LOW:
742 irq_type = OWL_GPIO_INT_LEVEL_LOW;
743 break;
744
745 default:
746 break;
747 }
748
749 port = owl_gpio_get_port(pctrl, &gpio);
750 if (WARN_ON(port == NULL))
751 return;
752
753 gpio_base = pctrl->base + port->offset;
754
755 raw_spin_lock_irqsave(&pctrl->lock, flags);
756
757 offset = (gpio < 16) ? 4 : 0;
758 value = readl_relaxed(gpio_base + port->intc_type + offset);
759 value &= ~(OWL_GPIO_INT_MASK << ((gpio % 16) * 2));
760 value |= irq_type << ((gpio % 16) * 2);
761 writel_relaxed(value, gpio_base + port->intc_type + offset);
762
763 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
764}
765
766static void owl_gpio_irq_mask(struct irq_data *data)
767{
768 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
769 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
770 const struct owl_gpio_port *port;
771 void __iomem *gpio_base;
772 unsigned long flags;
773 unsigned int gpio = data->hwirq;
774 u32 val;
775
776 port = owl_gpio_get_port(pctrl, &gpio);
777 if (WARN_ON(port == NULL))
778 return;
779
780 gpio_base = pctrl->base + port->offset;
781
782 raw_spin_lock_irqsave(&pctrl->lock, flags);
783
784 owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, false);
785
786 /* disable port interrupt if no interrupt pending bit is active */
787 val = readl_relaxed(gpio_base + port->intc_msk);
788 if (val == 0)
789 owl_gpio_update_reg(gpio_base + port->intc_ctl,
790 OWL_GPIO_CTLR_ENABLE, false);
791
792 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
793}
794
795static void owl_gpio_irq_unmask(struct irq_data *data)
796{
797 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
798 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
799 const struct owl_gpio_port *port;
800 void __iomem *gpio_base;
801 unsigned long flags;
802 unsigned int gpio = data->hwirq;
803 u32 value;
804
805 port = owl_gpio_get_port(pctrl, &gpio);
806 if (WARN_ON(port == NULL))
807 return;
808
809 gpio_base = pctrl->base + port->offset;
810 raw_spin_lock_irqsave(&pctrl->lock, flags);
811
812 /* enable port interrupt */
813 value = readl_relaxed(gpio_base + port->intc_ctl);
814 value |= BIT(OWL_GPIO_CTLR_ENABLE) | BIT(OWL_GPIO_CTLR_SAMPLE_CLK_24M);
815 writel_relaxed(value, gpio_base + port->intc_ctl);
816
817 /* enable GPIO interrupt */
818 owl_gpio_update_reg(gpio_base + port->intc_msk, gpio, true);
819
820 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
821}
822
823static void owl_gpio_irq_ack(struct irq_data *data)
824{
825 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
826 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
827 const struct owl_gpio_port *port;
828 void __iomem *gpio_base;
829 unsigned long flags;
830 unsigned int gpio = data->hwirq;
831
832 /*
833 * Switch the interrupt edge to the opposite edge of the interrupt
834 * which got triggered for the case of emulating both edges
835 */
836 if (irqd_get_trigger_type(data) == IRQ_TYPE_EDGE_BOTH) {
837 if (owl_gpio_get(gc, gpio))
838 irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING);
839 else
840 irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING);
841 }
842
843 port = owl_gpio_get_port(pctrl, &gpio);
844 if (WARN_ON(port == NULL))
845 return;
846
847 gpio_base = pctrl->base + port->offset;
848
849 raw_spin_lock_irqsave(&pctrl->lock, flags);
850
851 owl_gpio_update_reg(gpio_base + port->intc_ctl,
852 OWL_GPIO_CTLR_PENDING, true);
853
854 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
855}
856
857static int owl_gpio_irq_set_type(struct irq_data *data, unsigned int type)
858{
859 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
860 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
861
862 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
863 irq_set_handler_locked(data, handle_level_irq);
864 else
865 irq_set_handler_locked(data, handle_edge_irq);
866
867 irq_set_type(pctrl, data->hwirq, type);
868
869 return 0;
870}
871
872static void owl_gpio_irq_handler(struct irq_desc *desc)
873{
874 struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc);
875 struct irq_chip *chip = irq_desc_get_chip(desc);
876 struct irq_domain *domain = pctrl->chip.irq.domain;
877 unsigned int parent = irq_desc_get_irq(desc);
878 const struct owl_gpio_port *port;
879 void __iomem *base;
880 unsigned int pin, irq, offset = 0, i;
881 unsigned long pending_irq;
882
883 chained_irq_enter(chip, desc);
884
885 for (i = 0; i < pctrl->soc->nports; i++) {
886 port = &pctrl->soc->ports[i];
887 base = pctrl->base + port->offset;
888
889 /* skip ports that are not associated with this irq */
890 if (parent != pctrl->irq[i])
891 goto skip;
892
893 pending_irq = readl_relaxed(base + port->intc_pd);
894
895 for_each_set_bit(pin, &pending_irq, port->pins) {
896 irq = irq_find_mapping(domain, offset + pin);
897 generic_handle_irq(irq);
898
899 /* clear pending interrupt */
900 owl_gpio_update_reg(base + port->intc_pd, pin, true);
901 }
902
903skip:
904 offset += port->pins;
905 }
906
907 chained_irq_exit(chip, desc);
908}
909
704static int owl_gpio_init(struct owl_pinctrl *pctrl)
705{
706 struct gpio_chip *chip;
910static int owl_gpio_init(struct owl_pinctrl *pctrl)
911{
912 struct gpio_chip *chip;
707 int ret;
913 struct gpio_irq_chip *gpio_irq;
914 int ret, i, j, offset;
708
709 chip = &pctrl->chip;
710 chip->base = -1;
711 chip->ngpio = pctrl->soc->ngpios;
712 chip->label = dev_name(pctrl->dev);
713 chip->parent = pctrl->dev;
714 chip->owner = THIS_MODULE;
715 chip->of_node = pctrl->dev->of_node;
716
915
916 chip = &pctrl->chip;
917 chip->base = -1;
918 chip->ngpio = pctrl->soc->ngpios;
919 chip->label = dev_name(pctrl->dev);
920 chip->parent = pctrl->dev;
921 chip->owner = THIS_MODULE;
922 chip->of_node = pctrl->dev->of_node;
923
924 pctrl->irq_chip.name = chip->of_node->name;
925 pctrl->irq_chip.irq_ack = owl_gpio_irq_ack;
926 pctrl->irq_chip.irq_mask = owl_gpio_irq_mask;
927 pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask;
928 pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type;
929
930 gpio_irq = &chip->irq;
931 gpio_irq->chip = &pctrl->irq_chip;
932 gpio_irq->handler = handle_simple_irq;
933 gpio_irq->default_type = IRQ_TYPE_NONE;
934 gpio_irq->parent_handler = owl_gpio_irq_handler;
935 gpio_irq->parent_handler_data = pctrl;
936 gpio_irq->num_parents = pctrl->num_irq;
937 gpio_irq->parents = pctrl->irq;
938
939 gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio,
940 sizeof(*gpio_irq->map), GFP_KERNEL);
941 if (!gpio_irq->map)
942 return -ENOMEM;
943
944 for (i = 0, offset = 0; i < pctrl->soc->nports; i++) {
945 const struct owl_gpio_port *port = &pctrl->soc->ports[i];
946
947 for (j = 0; j < port->pins; j++)
948 gpio_irq->map[offset + j] = gpio_irq->parents[i];
949
950 offset += port->pins;
951 }
952
717 ret = gpiochip_add_data(&pctrl->chip, pctrl);
718 if (ret) {
719 dev_err(pctrl->dev, "failed to register gpiochip\n");
720 return ret;
721 }
722
723 return 0;
724}
725
726int owl_pinctrl_probe(struct platform_device *pdev,
727 struct owl_pinctrl_soc_data *soc_data)
728{
729 struct resource *res;
730 struct owl_pinctrl *pctrl;
953 ret = gpiochip_add_data(&pctrl->chip, pctrl);
954 if (ret) {
955 dev_err(pctrl->dev, "failed to register gpiochip\n");
956 return ret;
957 }
958
959 return 0;
960}
961
962int owl_pinctrl_probe(struct platform_device *pdev,
963 struct owl_pinctrl_soc_data *soc_data)
964{
965 struct resource *res;
966 struct owl_pinctrl *pctrl;
731 int ret;
967 int ret, i;
732
733 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
734 if (!pctrl)
735 return -ENOMEM;
736
737 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
738 pctrl->base = devm_ioremap_resource(&pdev->dev, res);
739 if (IS_ERR(pctrl->base))

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767
768 pctrl->soc = soc_data;
769 pctrl->dev = &pdev->dev;
770
771 pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
772 &owl_pinctrl_desc, pctrl);
773 if (IS_ERR(pctrl->pctrldev)) {
774 dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
968
969 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
970 if (!pctrl)
971 return -ENOMEM;
972
973 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
974 pctrl->base = devm_ioremap_resource(&pdev->dev, res);
975 if (IS_ERR(pctrl->base))

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1003
1004 pctrl->soc = soc_data;
1005 pctrl->dev = &pdev->dev;
1006
1007 pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
1008 &owl_pinctrl_desc, pctrl);
1009 if (IS_ERR(pctrl->pctrldev)) {
1010 dev_err(&pdev->dev, "could not register Actions OWL pinmux driver\n");
775 return PTR_ERR(pctrl->pctrldev);
1011 ret = PTR_ERR(pctrl->pctrldev);
1012 goto err_exit;
776 }
777
1013 }
1014
1015 ret = platform_irq_count(pdev);
1016 if (ret < 0)
1017 goto err_exit;
1018
1019 pctrl->num_irq = ret;
1020
1021 pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq,
1022 sizeof(*pctrl->irq), GFP_KERNEL);
1023 if (!pctrl->irq) {
1024 ret = -ENOMEM;
1025 goto err_exit;
1026 }
1027
1028 for (i = 0; i < pctrl->num_irq ; i++) {
1029 pctrl->irq[i] = platform_get_irq(pdev, i);
1030 if (pctrl->irq[i] < 0) {
1031 ret = pctrl->irq[i];
1032 goto err_exit;
1033 }
1034 }
1035
778 ret = owl_gpio_init(pctrl);
779 if (ret)
1036 ret = owl_gpio_init(pctrl);
1037 if (ret)
780 return ret;
1038 goto err_exit;
781
782 platform_set_drvdata(pdev, pctrl);
783
784 return 0;
1039
1040 platform_set_drvdata(pdev, pctrl);
1041
1042 return 0;
1043
1044err_exit:
1045 clk_disable_unprepare(pctrl->clk);
1046
1047 return ret;
785}
1048}