| phy-zynqmp.c (762f99f4f3cb41a775b5157dd761217beba65873) | phy-zynqmp.c (37291f60d0822f191748c2a54ce63b0bc669020f) |
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| 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT. 4 * 5 * Copyright (C) 2018-2020 Xilinx Inc. 6 * 7 * Author: Anurag Kumar Vulisha <anuragku@xilinx.com> 8 * Author: Subbaraya Sundeep <sundeep.lkml@gmail.com> --- 120 unchanged lines hidden (view full) --- 129#define TM_CMN_RST_MASK 0x3 130 131/* Bus width parameters */ 132#define TX_PROT_BUS_WIDTH 0x10040 133#define RX_PROT_BUS_WIDTH 0x10044 134#define PROT_BUS_WIDTH_10 0x0 135#define PROT_BUS_WIDTH_20 0x1 136#define PROT_BUS_WIDTH_40 0x2 | 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT. 4 * 5 * Copyright (C) 2018-2020 Xilinx Inc. 6 * 7 * Author: Anurag Kumar Vulisha <anuragku@xilinx.com> 8 * Author: Subbaraya Sundeep <sundeep.lkml@gmail.com> --- 120 unchanged lines hidden (view full) --- 129#define TM_CMN_RST_MASK 0x3 130 131/* Bus width parameters */ 132#define TX_PROT_BUS_WIDTH 0x10040 133#define RX_PROT_BUS_WIDTH 0x10044 134#define PROT_BUS_WIDTH_10 0x0 135#define PROT_BUS_WIDTH_20 0x1 136#define PROT_BUS_WIDTH_40 0x2 |
| 137#define PROT_BUS_WIDTH_SHIFT 2 | 137#define PROT_BUS_WIDTH_SHIFT(n) ((n) * 2) 138#define PROT_BUS_WIDTH_MASK(n) GENMASK((n) * 2 + 1, (n) * 2) |
| 138 139/* Number of GT lanes */ 140#define NUM_LANES 4 141 142/* SIOU SATA control register */ 143#define SATA_CONTROL_OFFSET 0x0100 144 145/* Total number of controllers */ --- 294 unchanged lines hidden (view full) --- 440 441 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET); 442} 443 444/* SGMII-specific initialization. */ 445static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy) 446{ 447 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; | 139 140/* Number of GT lanes */ 141#define NUM_LANES 4 142 143/* SIOU SATA control register */ 144#define SATA_CONTROL_OFFSET 0x0100 145 146/* Total number of controllers */ --- 294 unchanged lines hidden (view full) --- 441 442 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET); 443} 444 445/* SGMII-specific initialization. */ 446static void xpsgtr_phy_init_sgmii(struct xpsgtr_phy *gtr_phy) 447{ 448 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; |
| 449 u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane); 450 u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane); |
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| 448 449 /* Set SGMII protocol TX and RX bus width to 10 bits. */ | 451 452 /* Set SGMII protocol TX and RX bus width to 10 bits. */ |
| 450 xpsgtr_write(gtr_dev, TX_PROT_BUS_WIDTH, 451 PROT_BUS_WIDTH_10 << (gtr_phy->lane * PROT_BUS_WIDTH_SHIFT)); 452 xpsgtr_write(gtr_dev, RX_PROT_BUS_WIDTH, 453 PROT_BUS_WIDTH_10 << (gtr_phy->lane * PROT_BUS_WIDTH_SHIFT)); | 453 xpsgtr_clr_set(gtr_dev, TX_PROT_BUS_WIDTH, mask, val); 454 xpsgtr_clr_set(gtr_dev, RX_PROT_BUS_WIDTH, mask, val); |
| 454 455 xpsgtr_bypass_scrambler_8b10b(gtr_phy); 456} 457 458/* Configure TX de-emphasis and margining for DP. */ 459static void xpsgtr_phy_configure_dp(struct xpsgtr_phy *gtr_phy, unsigned int pre, 460 unsigned int voltage) 461{ --- 576 unchanged lines hidden --- | 455 456 xpsgtr_bypass_scrambler_8b10b(gtr_phy); 457} 458 459/* Configure TX de-emphasis and margining for DP. */ 460static void xpsgtr_phy_configure_dp(struct xpsgtr_phy *gtr_phy, unsigned int pre, 461 unsigned int voltage) 462{ --- 576 unchanged lines hidden --- |