phy-zynqmp.c (687d6bccb28238fcfa65f7c1badfdfeac498c428) phy-zynqmp.c (6959d2367bc3503ac4ba3eb4ec6584a43150d6b3)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
4 *
5 * Copyright (C) 2018-2020 Xilinx Inc.
6 *
7 * Author: Anurag Kumar Vulisha <anuragku@xilinx.com>
8 * Author: Subbaraya Sundeep <sundeep.lkml@gmail.com>

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142#define NUM_LANES 4
143
144/* SIOU SATA control register */
145#define SATA_CONTROL_OFFSET 0x0100
146
147/* Total number of controllers */
148#define CONTROLLERS_PER_LANE 5
149
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
4 *
5 * Copyright (C) 2018-2020 Xilinx Inc.
6 *
7 * Author: Anurag Kumar Vulisha <anuragku@xilinx.com>
8 * Author: Subbaraya Sundeep <sundeep.lkml@gmail.com>

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142#define NUM_LANES 4
143
144/* SIOU SATA control register */
145#define SATA_CONTROL_OFFSET 0x0100
146
147/* Total number of controllers */
148#define CONTROLLERS_PER_LANE 5
149
150/* Protocol Type parameters */
151#define XPSGTR_TYPE_USB0 0 /* USB controller 0 */
152#define XPSGTR_TYPE_USB1 1 /* USB controller 1 */
153#define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
154#define XPSGTR_TYPE_SATA_1 3 /* SATA controller lane 1 */
155#define XPSGTR_TYPE_PCIE_0 4 /* PCIe controller lane 0 */
156#define XPSGTR_TYPE_PCIE_1 5 /* PCIe controller lane 1 */
157#define XPSGTR_TYPE_PCIE_2 6 /* PCIe controller lane 2 */
158#define XPSGTR_TYPE_PCIE_3 7 /* PCIe controller lane 3 */
159#define XPSGTR_TYPE_DP_0 8 /* Display Port controller lane 0 */
160#define XPSGTR_TYPE_DP_1 9 /* Display Port controller lane 1 */
161#define XPSGTR_TYPE_SGMII0 10 /* Ethernet SGMII controller 0 */
162#define XPSGTR_TYPE_SGMII1 11 /* Ethernet SGMII controller 1 */
163#define XPSGTR_TYPE_SGMII2 12 /* Ethernet SGMII controller 2 */
164#define XPSGTR_TYPE_SGMII3 13 /* Ethernet SGMII controller 3 */
165
166/* Timeout values */
167#define TIMEOUT_US 1000
168
169struct xpsgtr_dev;
170
171/**
172 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
173 * @refclk_rate: PLL reference clock frequency

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180 u8 pll_ref_clk;
181 u32 steps;
182 u32 step_size;
183};
184
185/**
186 * struct xpsgtr_phy - representation of a lane
187 * @phy: pointer to the kernel PHY device
150/* Timeout values */
151#define TIMEOUT_US 1000
152
153struct xpsgtr_dev;
154
155/**
156 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
157 * @refclk_rate: PLL reference clock frequency

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164 u8 pll_ref_clk;
165 u32 steps;
166 u32 step_size;
167};
168
169/**
170 * struct xpsgtr_phy - representation of a lane
171 * @phy: pointer to the kernel PHY device
188 * @type: controller which uses this lane
172 * @instance: instance of the protocol type (such as the lane within a
173 * protocol, or the USB/Ethernet controller)
189 * @lane: lane number
190 * @protocol: protocol in which the lane operates
191 * @skip_phy_init: skip phy_init() if true
192 * @dev: pointer to the xpsgtr_dev instance
193 * @refclk: reference clock index
194 */
195struct xpsgtr_phy {
196 struct phy *phy;
174 * @lane: lane number
175 * @protocol: protocol in which the lane operates
176 * @skip_phy_init: skip phy_init() if true
177 * @dev: pointer to the xpsgtr_dev instance
178 * @refclk: reference clock index
179 */
180struct xpsgtr_phy {
181 struct phy *phy;
197 u8 type;
182 u8 instance;
198 u8 lane;
199 u8 protocol;
200 bool skip_phy_init;
201 struct xpsgtr_dev *dev;
202 unsigned int refclk;
203};
204
205/**

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326 break;
327 }
328
329 udelay(1);
330 }
331
332 if (ret == -ETIMEDOUT)
333 dev_err(gtr_dev->dev,
183 u8 lane;
184 u8 protocol;
185 bool skip_phy_init;
186 struct xpsgtr_dev *dev;
187 unsigned int refclk;
188};
189
190/**

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311 break;
312 }
313
314 udelay(1);
315 }
316
317 if (ret == -ETIMEDOUT)
318 dev_err(gtr_dev->dev,
334 "lane %u (type %u, protocol %u): PLL lock timeout\n",
335 gtr_phy->lane, gtr_phy->type, gtr_phy->protocol);
319 "lane %u (protocol %u, instance %u): PLL lock timeout\n",
320 gtr_phy->lane, gtr_phy->protocol, gtr_phy->instance);
336
337 return ret;
338}
339
340/* Configure PLL and spread-sprectrum clock. */
341static void xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy)
342{
343 const struct xpsgtr_ssc *ssc;

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640 /* Skip initialization if not required. */
641 if (!xpsgtr_phy_init_required(gtr_phy))
642 return ret;
643 /*
644 * Wait for the PLL to lock. For DP, only wait on DP0 to avoid
645 * cumulating waits for both lanes. The user is expected to initialize
646 * lane 0 last.
647 */
321
322 return ret;
323}
324
325/* Configure PLL and spread-sprectrum clock. */
326static void xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy)
327{
328 const struct xpsgtr_ssc *ssc;

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625 /* Skip initialization if not required. */
626 if (!xpsgtr_phy_init_required(gtr_phy))
627 return ret;
628 /*
629 * Wait for the PLL to lock. For DP, only wait on DP0 to avoid
630 * cumulating waits for both lanes. The user is expected to initialize
631 * lane 0 last.
632 */
648 if (gtr_phy->protocol != ICM_PROTOCOL_DP ||
649 gtr_phy->type == XPSGTR_TYPE_DP_0)
633 if (gtr_phy->protocol != ICM_PROTOCOL_DP || !gtr_phy->instance)
650 ret = xpsgtr_wait_pll_lock(phy);
651
652 return ret;
653}
654
655static int xpsgtr_phy_configure(struct phy *phy, union phy_configure_opts *opts)
656{
657 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);

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671 .configure = xpsgtr_phy_configure,
672 .owner = THIS_MODULE,
673};
674
675/*
676 * OF Xlate Support
677 */
678
634 ret = xpsgtr_wait_pll_lock(phy);
635
636 return ret;
637}
638
639static int xpsgtr_phy_configure(struct phy *phy, union phy_configure_opts *opts)
640{
641 struct xpsgtr_phy *gtr_phy = phy_get_drvdata(phy);

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655 .configure = xpsgtr_phy_configure,
656 .owner = THIS_MODULE,
657};
658
659/*
660 * OF Xlate Support
661 */
662
679/* Set the lane type and protocol based on the PHY type and instance number. */
663/* Set the lane protocol and instance based on the PHY type and instance number. */
680static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type,
681 unsigned int phy_instance)
682{
683 unsigned int num_phy_types;
664static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type,
665 unsigned int phy_instance)
666{
667 unsigned int num_phy_types;
684 const int *phy_types;
685
686 switch (phy_type) {
668
669 switch (phy_type) {
687 case PHY_TYPE_SATA: {
688 static const int types[] = {
689 XPSGTR_TYPE_SATA_0,
690 XPSGTR_TYPE_SATA_1,
691 };
692
693 phy_types = types;
694 num_phy_types = ARRAY_SIZE(types);
670 case PHY_TYPE_SATA:
671 num_phy_types = 2;
695 gtr_phy->protocol = ICM_PROTOCOL_SATA;
696 break;
672 gtr_phy->protocol = ICM_PROTOCOL_SATA;
673 break;
697 }
698 case PHY_TYPE_USB3: {
699 static const int types[] = {
700 XPSGTR_TYPE_USB0,
701 XPSGTR_TYPE_USB1,
702 };
703
704 phy_types = types;
705 num_phy_types = ARRAY_SIZE(types);
674 case PHY_TYPE_USB3:
675 num_phy_types = 2;
706 gtr_phy->protocol = ICM_PROTOCOL_USB;
707 break;
676 gtr_phy->protocol = ICM_PROTOCOL_USB;
677 break;
708 }
709 case PHY_TYPE_DP: {
710 static const int types[] = {
711 XPSGTR_TYPE_DP_0,
712 XPSGTR_TYPE_DP_1,
713 };
714
715 phy_types = types;
716 num_phy_types = ARRAY_SIZE(types);
678 case PHY_TYPE_DP:
679 num_phy_types = 2;
717 gtr_phy->protocol = ICM_PROTOCOL_DP;
718 break;
680 gtr_phy->protocol = ICM_PROTOCOL_DP;
681 break;
719 }
720 case PHY_TYPE_PCIE: {
721 static const int types[] = {
722 XPSGTR_TYPE_PCIE_0,
723 XPSGTR_TYPE_PCIE_1,
724 XPSGTR_TYPE_PCIE_2,
725 XPSGTR_TYPE_PCIE_3,
726 };
727
728 phy_types = types;
729 num_phy_types = ARRAY_SIZE(types);
682 case PHY_TYPE_PCIE:
683 num_phy_types = 4;
730 gtr_phy->protocol = ICM_PROTOCOL_PCIE;
731 break;
684 gtr_phy->protocol = ICM_PROTOCOL_PCIE;
685 break;
732 }
733 case PHY_TYPE_SGMII: {
734 static const int types[] = {
735 XPSGTR_TYPE_SGMII0,
736 XPSGTR_TYPE_SGMII1,
737 XPSGTR_TYPE_SGMII2,
738 XPSGTR_TYPE_SGMII3,
739 };
740
741 phy_types = types;
742 num_phy_types = ARRAY_SIZE(types);
686 case PHY_TYPE_SGMII:
687 num_phy_types = 4;
743 gtr_phy->protocol = ICM_PROTOCOL_SGMII;
744 break;
688 gtr_phy->protocol = ICM_PROTOCOL_SGMII;
689 break;
745 }
746 default:
747 return -EINVAL;
748 }
749
750 if (phy_instance >= num_phy_types)
751 return -EINVAL;
752
690 default:
691 return -EINVAL;
692 }
693
694 if (phy_instance >= num_phy_types)
695 return -EINVAL;
696
753 gtr_phy->type = phy_types[phy_instance];
697 gtr_phy->instance = phy_instance;
754 return 0;
755}
756
757/*
698 return 0;
699}
700
701/*
758 * Valid combinations of controllers and lanes (Interconnect Matrix).
702 * Valid combinations of controllers and lanes (Interconnect Matrix). Each
703 * "instance" represents one controller for a lane. For PCIe and DP, the
704 * "instance" is the logical lane in the link. For SATA, USB, and SGMII,
705 * the instance is the index of the controller.
706 *
707 * This information is only used to validate the devicetree reference, and is
708 * not used when programming the hardware.
759 */
760static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = {
709 */
710static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = {
761 { XPSGTR_TYPE_PCIE_0, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
762 XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII0 },
763 { XPSGTR_TYPE_PCIE_1, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB0,
764 XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII1 },
765 { XPSGTR_TYPE_PCIE_2, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
766 XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII2 },
767 { XPSGTR_TYPE_PCIE_3, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB1,
768 XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII3 }
711 /* PCIe, SATA, USB, DP, SGMII */
712 { 0, 0, 0, 1, 0 }, /* Lane 0 */
713 { 1, 1, 0, 0, 1 }, /* Lane 1 */
714 { 2, 0, 0, 1, 2 }, /* Lane 2 */
715 { 3, 1, 1, 0, 3 }, /* Lane 3 */
769};
770
771/* Translate OF phandle and args to PHY instance. */
772static struct phy *xpsgtr_xlate(struct device *dev,
773 const struct of_phandle_args *args)
774{
775 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
776 struct xpsgtr_phy *gtr_phy;

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815
816 gtr_phy->refclk = refclk;
817
818 /*
819 * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type
820 * is allowed to operate on the lane.
821 */
822 for (i = 0; i < CONTROLLERS_PER_LANE; i++) {
716};
717
718/* Translate OF phandle and args to PHY instance. */
719static struct phy *xpsgtr_xlate(struct device *dev,
720 const struct of_phandle_args *args)
721{
722 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
723 struct xpsgtr_phy *gtr_phy;

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762
763 gtr_phy->refclk = refclk;
764
765 /*
766 * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type
767 * is allowed to operate on the lane.
768 */
769 for (i = 0; i < CONTROLLERS_PER_LANE; i++) {
823 if (icm_matrix[phy_lane][i] == gtr_phy->type)
770 if (icm_matrix[phy_lane][i] == gtr_phy->instance)
824 return gtr_phy->phy;
825 }
826
827 return ERR_PTR(-EINVAL);
828}
829
830/*
831 * Power Management

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772 }
773
774 return ERR_PTR(-EINVAL);
775}
776
777/*
778 * Power Management

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