phy-zynqmp.c (4a33bea003144e217d8a3ae666f171dfc2e97bd6) phy-zynqmp.c (1c59c2d95d3160a2af4a8655d19f56648b2dffa3)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
4 *
5 * Copyright (C) 2018-2020 Xilinx Inc.
6 *
7 * Author: Anurag Kumar Vulisha <anuragku@xilinx.com>
8 * Author: Subbaraya Sundeep <sundeep.lkml@gmail.com>

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810
811 return ERR_PTR(-EINVAL);
812}
813
814/*
815 * Power Management
816 */
817
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
4 *
5 * Copyright (C) 2018-2020 Xilinx Inc.
6 *
7 * Author: Anurag Kumar Vulisha <anuragku@xilinx.com>
8 * Author: Subbaraya Sundeep <sundeep.lkml@gmail.com>

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810
811 return ERR_PTR(-EINVAL);
812}
813
814/*
815 * Power Management
816 */
817
818#ifdef CONFIG_PM
819static int xpsgtr_suspend(struct device *dev)
818static int __maybe_unused xpsgtr_suspend(struct device *dev)
820{
821 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
822
823 /* Save the snapshot ICM_CFG registers. */
824 gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
825 gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
826
827 return 0;
828}
829
819{
820 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
821
822 /* Save the snapshot ICM_CFG registers. */
823 gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
824 gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);
825
826 return 0;
827}
828
830static int xpsgtr_resume(struct device *dev)
829static int __maybe_unused xpsgtr_resume(struct device *dev)
831{
832 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
833 unsigned int icm_cfg0, icm_cfg1;
834 unsigned int i;
835 bool skip_phy_init;
836
837 icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
838 icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);

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849 skip_phy_init = false;
850
851 /* Update the skip_phy_init for all gtr_phy instances. */
852 for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++)
853 gtr_dev->phys[i].skip_phy_init = skip_phy_init;
854
855 return 0;
856}
830{
831 struct xpsgtr_dev *gtr_dev = dev_get_drvdata(dev);
832 unsigned int icm_cfg0, icm_cfg1;
833 unsigned int i;
834 bool skip_phy_init;
835
836 icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0);
837 icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1);

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848 skip_phy_init = false;
849
850 /* Update the skip_phy_init for all gtr_phy instances. */
851 for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++)
852 gtr_dev->phys[i].skip_phy_init = skip_phy_init;
853
854 return 0;
855}
857#endif /* CONFIG_PM */
858
859static const struct dev_pm_ops xpsgtr_pm_ops = {
860 SET_SYSTEM_SLEEP_PM_OPS(xpsgtr_suspend, xpsgtr_resume)
861};
862
863/*
864 * Probe & Platform Driver
865 */

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857static const struct dev_pm_ops xpsgtr_pm_ops = {
858 SET_SYSTEM_SLEEP_PM_OPS(xpsgtr_suspend, xpsgtr_resume)
859};
860
861/*
862 * Probe & Platform Driver
863 */

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