cxl_pmu.c (f0bae243b2bcf2b160ae547463bf542762beef8f) cxl_pmu.c (b91b73a43822566930490e5aa421ccb1900a2124)
1// SPDX-License-Identifier: GPL-2.0-only
2
3/*
4 * Copyright(c) 2023 Huawei
5 *
6 * The CXL 3.0 specification includes a standard Performance Monitoring Unit,
7 * called the CXL PMU, or CPMU. In order to allow a high degree of
8 * implementation flexibility the specification provides a wide range of

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203 pmu_ev->event_idx = j;
204 list_add(&pmu_ev->node, &info->event_caps_configurable);
205 }
206 }
207
208 return 0;
209}
210
1// SPDX-License-Identifier: GPL-2.0-only
2
3/*
4 * Copyright(c) 2023 Huawei
5 *
6 * The CXL 3.0 specification includes a standard Performance Monitoring Unit,
7 * called the CXL PMU, or CPMU. In order to allow a high degree of
8 * implementation flexibility the specification provides a wide range of

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203 pmu_ev->event_idx = j;
204 list_add(&pmu_ev->node, &info->event_caps_configurable);
205 }
206 }
207
208 return 0;
209}
210
211static ssize_t cxl_pmu_format_sysfs_show(struct device *dev,
212 struct device_attribute *attr, char *buf)
213{
214 struct dev_ext_attribute *eattr;
215
216 eattr = container_of(attr, struct dev_ext_attribute, attr);
217
218 return sysfs_emit(buf, "%s\n", (char *)eattr->var);
219}
220
221#define CXL_PMU_FORMAT_ATTR(_name, _format)\
222 (&((struct dev_ext_attribute[]) { \
223 { \
211#define CXL_PMU_FORMAT_ATTR(_name, _format)\
212 (&((struct dev_ext_attribute[]) { \
213 { \
224 .attr = __ATTR(_name, 0444, \
225 cxl_pmu_format_sysfs_show, NULL), \
214 .attr = __ATTR(_name, 0444, device_show_string, NULL), \
226 .var = (void *)_format \
227 } \
228 })[0].attr.attr)
229
230enum {
231 cxl_pmu_mask_attr,
232 cxl_pmu_gid_attr,
233 cxl_pmu_vid_attr,

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340}
341
342#define CXL_PMU_EVENT_ATTR(_name, _vid, _gid, _msk) \
343 PMU_EVENT_ATTR_ID(_name, cxl_pmu_event_sysfs_show, \
344 ((u64)(_vid) << 48) | ((u64)(_gid) << 32) | (u64)(_msk))
345
346/* For CXL spec defined events */
347#define CXL_PMU_EVENT_CXL_ATTR(_name, _gid, _msk) \
215 .var = (void *)_format \
216 } \
217 })[0].attr.attr)
218
219enum {
220 cxl_pmu_mask_attr,
221 cxl_pmu_gid_attr,
222 cxl_pmu_vid_attr,

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329}
330
331#define CXL_PMU_EVENT_ATTR(_name, _vid, _gid, _msk) \
332 PMU_EVENT_ATTR_ID(_name, cxl_pmu_event_sysfs_show, \
333 ((u64)(_vid) << 48) | ((u64)(_gid) << 32) | (u64)(_msk))
334
335/* For CXL spec defined events */
336#define CXL_PMU_EVENT_CXL_ATTR(_name, _gid, _msk) \
348 CXL_PMU_EVENT_ATTR(_name, PCI_VENDOR_ID_CXL, _gid, _msk)
337 CXL_PMU_EVENT_ATTR(_name, PCI_DVSEC_VENDOR_ID_CXL, _gid, _msk)
349
350static struct attribute *cxl_pmu_event_attrs[] = {
351 CXL_PMU_EVENT_CXL_ATTR(clock_ticks, CXL_PMU_GID_CLOCK_TICKS, BIT(0)),
352 /* CXL rev 3.0 Table 3-17 - Device to Host Requests */
353 CXL_PMU_EVENT_CXL_ATTR(d2h_req_rdcurr, CXL_PMU_GID_D2H_REQ, BIT(1)),
354 CXL_PMU_EVENT_CXL_ATTR(d2h_req_rdown, CXL_PMU_GID_D2H_REQ, BIT(2)),
355 CXL_PMU_EVENT_CXL_ATTR(d2h_req_rdshared, CXL_PMU_GID_D2H_REQ, BIT(3)),
356 CXL_PMU_EVENT_CXL_ATTR(d2h_req_rdany, CXL_PMU_GID_D2H_REQ, BIT(4)),

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339static struct attribute *cxl_pmu_event_attrs[] = {
340 CXL_PMU_EVENT_CXL_ATTR(clock_ticks, CXL_PMU_GID_CLOCK_TICKS, BIT(0)),
341 /* CXL rev 3.0 Table 3-17 - Device to Host Requests */
342 CXL_PMU_EVENT_CXL_ATTR(d2h_req_rdcurr, CXL_PMU_GID_D2H_REQ, BIT(1)),
343 CXL_PMU_EVENT_CXL_ATTR(d2h_req_rdown, CXL_PMU_GID_D2H_REQ, BIT(2)),
344 CXL_PMU_EVENT_CXL_ATTR(d2h_req_rdshared, CXL_PMU_GID_D2H_REQ, BIT(3)),
345 CXL_PMU_EVENT_CXL_ATTR(d2h_req_rdany, CXL_PMU_GID_D2H_REQ, BIT(4)),

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