pcie-designware.h (57390019b68b83f96eb98f490367b9df1f2d77cb) pcie-designware.h (a78794562fcb2659c976388b1285eddda97e9954)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>

--- 287 unchanged lines hidden (view full) ---

296 DW_PCIE_LTSSM_L2_IDLE = 0x15,
297
298 DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF,
299};
300
301struct dw_pcie_host_ops {
302 int (*host_init)(struct dw_pcie_rp *pp);
303 void (*host_deinit)(struct dw_pcie_rp *pp);
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>

--- 287 unchanged lines hidden (view full) ---

296 DW_PCIE_LTSSM_L2_IDLE = 0x15,
297
298 DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF,
299};
300
301struct dw_pcie_host_ops {
302 int (*host_init)(struct dw_pcie_rp *pp);
303 void (*host_deinit)(struct dw_pcie_rp *pp);
304 void (*host_post_init)(struct dw_pcie_rp *pp);
304 int (*msi_host_init)(struct dw_pcie_rp *pp);
305 void (*pme_turn_off)(struct dw_pcie_rp *pp);
306};
307
308struct dw_pcie_rp {
309 bool has_msi_ctrl:1;
310 bool cfg0_io_shared:1;
311 u64 cfg0_base;

--- 334 unchanged lines hidden --- 		305 int (*msi_host_init)(struct dw_pcie_rp *pp);
306 void (*pme_turn_off)(struct dw_pcie_rp *pp);
307};
308
309struct dw_pcie_rp {
310 bool has_msi_ctrl:1;
311 bool cfg0_io_shared:1;
312 u64 cfg0_base;

--- 334 unchanged lines hidden ---