pcie-designware.h (47a062609a30d820aa2fe62450f0212f7f26b223) pcie-designware.h (07940c369a6bf940ec4a00eeb76bf51daa4f3973)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>

--- 176 unchanged lines hidden (view full) ---

185 resource_size_t io_base;
186 phys_addr_t io_bus_addr;
187 u32 io_size;
188 int irq;
189 const struct dw_pcie_host_ops *ops;
190 int msi_irq;
191 struct irq_domain *irq_domain;
192 struct irq_domain *msi_domain;
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Synopsys DesignWare PCIe host controller driver
4 *
5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
6 * https://www.samsung.com
7 *
8 * Author: Jingoo Han <jg1.han@samsung.com>

--- 176 unchanged lines hidden (view full) ---

185 resource_size_t io_base;
186 phys_addr_t io_bus_addr;
187 u32 io_size;
188 int irq;
189 const struct dw_pcie_host_ops *ops;
190 int msi_irq;
191 struct irq_domain *irq_domain;
192 struct irq_domain *msi_domain;
193 u16 msi_msg;
193 dma_addr_t msi_data;
194 dma_addr_t msi_data;
194 struct page *msi_page;
195 struct irq_chip *msi_irq_chip;
196 u32 num_vectors;
197 u32 irq_mask[MAX_MSI_CTRLS];
198 struct pci_host_bridge *bridge;
199 raw_spinlock_t lock;
200 DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
201};
202

--- 286 unchanged lines hidden --- 		195 struct irq_chip *msi_irq_chip;
196 u32 num_vectors;
197 u32 irq_mask[MAX_MSI_CTRLS];
198 struct pci_host_bridge *bridge;
199 raw_spinlock_t lock;
200 DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
201};
202

--- 286 unchanged lines hidden ---