pci-dra7xx.c (19b7858c3357df038d896c10e0d5e4572a77dd25) pci-dra7xx.c (db388348acffe954656ec38440809ec770707417)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
4 *
5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Kishon Vijay Abraham I <kishon@ti.com>
8 */

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173}
174
175static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
176{
177 dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
178 dra7xx_pcie_enable_msi_interrupts(dra7xx);
179}
180
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
4 *
5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Kishon Vijay Abraham I <kishon@ti.com>
8 */

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173}
174
175static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
176{
177 dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
178 dra7xx_pcie_enable_msi_interrupts(dra7xx);
179}
180
181static int dra7xx_pcie_host_init(struct pcie_port *pp)
181static int dra7xx_pcie_host_init(struct dw_pcie_rp *pp)
182{
183 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
184 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
185
186 dra7xx_pcie_enable_interrupts(dra7xx);
187
188 return 0;
189}

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197 return 0;
198}
199
200static const struct irq_domain_ops intx_domain_ops = {
201 .map = dra7xx_pcie_intx_map,
202 .xlate = pci_irqd_intx_xlate,
203};
204
182{
183 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
184 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
185
186 dra7xx_pcie_enable_interrupts(dra7xx);
187
188 return 0;
189}

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197 return 0;
198}
199
200static const struct irq_domain_ops intx_domain_ops = {
201 .map = dra7xx_pcie_intx_map,
202 .xlate = pci_irqd_intx_xlate,
203};
204
205static int dra7xx_pcie_handle_msi(struct pcie_port *pp, int index)
205static int dra7xx_pcie_handle_msi(struct dw_pcie_rp *pp, int index)
206{
207 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
208 unsigned long val;
209 int pos;
210
211 val = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
212 (index * MSI_REG_CTRL_BLOCK_SIZE));
213 if (!val)

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219 (index * MAX_MSI_IRQS_PER_CTRL) + pos);
220 pos++;
221 pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, pos);
222 }
223
224 return 1;
225}
226
206{
207 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
208 unsigned long val;
209 int pos;
210
211 val = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS +
212 (index * MSI_REG_CTRL_BLOCK_SIZE));
213 if (!val)

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219 (index * MAX_MSI_IRQS_PER_CTRL) + pos);
220 pos++;
221 pos = find_next_bit(&val, MAX_MSI_IRQS_PER_CTRL, pos);
222 }
223
224 return 1;
225}
226
227static void dra7xx_pcie_handle_msi_irq(struct pcie_port *pp)
227static void dra7xx_pcie_handle_msi_irq(struct dw_pcie_rp *pp)
228{
229 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
230 int ret, i, count, num_ctrls;
231
232 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
233
234 /**
235 * Need to make sure all MSI status bits read 0 before exiting.

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250 dev_warn_ratelimited(pci->dev,
251 "Too many MSI IRQs to handle\n");
252}
253
254static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc)
255{
256 struct irq_chip *chip = irq_desc_get_chip(desc);
257 struct dra7xx_pcie *dra7xx;
228{
229 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
230 int ret, i, count, num_ctrls;
231
232 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
233
234 /**
235 * Need to make sure all MSI status bits read 0 before exiting.

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250 dev_warn_ratelimited(pci->dev,
251 "Too many MSI IRQs to handle\n");
252}
253
254static void dra7xx_pcie_msi_irq_handler(struct irq_desc *desc)
255{
256 struct irq_chip *chip = irq_desc_get_chip(desc);
257 struct dra7xx_pcie *dra7xx;
258 struct dw_pcie_rp *pp;
258 struct dw_pcie *pci;
259 struct dw_pcie *pci;
259 struct pcie_port *pp;
260 unsigned long reg;
261 u32 bit;
262
263 chained_irq_enter(chip, desc);
264
265 pp = irq_desc_get_handler_data(desc);
266 pci = to_dw_pcie_from_pp(pp);
267 dra7xx = to_dra7xx_pcie(pci);

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339 if (reg & CFG_MSE_EVT)
340 dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
341
342 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
343
344 return IRQ_HANDLED;
345}
346
260 unsigned long reg;
261 u32 bit;
262
263 chained_irq_enter(chip, desc);
264
265 pp = irq_desc_get_handler_data(desc);
266 pci = to_dw_pcie_from_pp(pp);
267 dra7xx = to_dra7xx_pcie(pci);

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339 if (reg & CFG_MSE_EVT)
340 dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
341
342 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
343
344 return IRQ_HANDLED;
345}
346
347static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
347static int dra7xx_pcie_init_irq_domain(struct dw_pcie_rp *pp)
348{
349 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
350 struct device *dev = pci->dev;
351 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
352 struct device_node *node = dev->of_node;
353 struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
354
355 if (!pcie_intc_node) {

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470 return 0;
471}
472
473static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
474 struct platform_device *pdev)
475{
476 int ret;
477 struct dw_pcie *pci = dra7xx->pci;
348{
349 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
350 struct device *dev = pci->dev;
351 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
352 struct device_node *node = dev->of_node;
353 struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
354
355 if (!pcie_intc_node) {

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470 return 0;
471}
472
473static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
474 struct platform_device *pdev)
475{
476 int ret;
477 struct dw_pcie *pci = dra7xx->pci;
478 struct pcie_port *pp = &pci->pp;
478 struct dw_pcie_rp *pp = &pci->pp;
479 struct device *dev = pci->dev;
480
481 pp->irq = platform_get_irq(pdev, 1);
482 if (pp->irq < 0)
483 return pp->irq;
484
485 /* MSI IRQ is muxed */
479 struct device *dev = pci->dev;
480
481 pp->irq = platform_get_irq(pdev, 1);
482 if (pp->irq < 0)
483 return pp->irq;
484
485 /* MSI IRQ is muxed */
486 pp->msi_irq = -ENODEV;
486 pp->msi_irq[0] = -ENODEV;
487
488 ret = dra7xx_pcie_init_irq_domain(pp);
489 if (ret < 0)
490 return ret;
491
492 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc_dbics");
493 if (IS_ERR(pci->dbi_base))
494 return PTR_ERR(pci->dbi_base);

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857
858err_link:
859 while (--i >= 0)
860 device_link_del(link[i]);
861
862 return ret;
863}
864
487
488 ret = dra7xx_pcie_init_irq_domain(pp);
489 if (ret < 0)
490 return ret;
491
492 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "rc_dbics");
493 if (IS_ERR(pci->dbi_base))
494 return PTR_ERR(pci->dbi_base);

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857
858err_link:
859 while (--i >= 0)
860 device_link_del(link[i]);
861
862 return ret;
863}
864
865#ifdef CONFIG_PM_SLEEP
865static int dra7xx_pcie_suspend(struct device *dev)
866{
867 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
868 struct dw_pcie *pci = dra7xx->pci;
869 u32 val;
870
871 if (dra7xx->mode != DW_PCIE_RC_TYPE)
872 return 0;

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913 ret = dra7xx_pcie_enable_phy(dra7xx);
914 if (ret) {
915 dev_err(dev, "failed to enable phy\n");
916 return ret;
917 }
918
919 return 0;
920}
866static int dra7xx_pcie_suspend(struct device *dev)
867{
868 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
869 struct dw_pcie *pci = dra7xx->pci;
870 u32 val;
871
872 if (dra7xx->mode != DW_PCIE_RC_TYPE)
873 return 0;

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914 ret = dra7xx_pcie_enable_phy(dra7xx);
915 if (ret) {
916 dev_err(dev, "failed to enable phy\n");
917 return ret;
918 }
919
920 return 0;
921}
922#endif
921
922static void dra7xx_pcie_shutdown(struct platform_device *pdev)
923{
924 struct device *dev = &pdev->dev;
925 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
926 int ret;
927
928 dra7xx_pcie_stop_link(dra7xx->pci);

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933
934 pm_runtime_disable(dev);
935 dra7xx_pcie_disable_phy(dra7xx);
936
937 clk_disable_unprepare(dra7xx->clk);
938}
939
940static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
923
924static void dra7xx_pcie_shutdown(struct platform_device *pdev)
925{
926 struct device *dev = &pdev->dev;
927 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
928 int ret;
929
930 dra7xx_pcie_stop_link(dra7xx->pci);

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935
936 pm_runtime_disable(dev);
937 dra7xx_pcie_disable_phy(dra7xx);
938
939 clk_disable_unprepare(dra7xx->clk);
940}
941
942static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
941 SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
942 NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
943 dra7xx_pcie_resume_noirq)
943 SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
944 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
945 dra7xx_pcie_resume_noirq)
944};
945
946static struct platform_driver dra7xx_pcie_driver = {
947 .probe = dra7xx_pcie_probe,
948 .driver = {
949 .name = "dra7-pcie",
950 .of_match_table = of_dra7xx_pcie_match,
951 .suppress_bind_attrs = true,
952 .pm = &dra7xx_pcie_pm_ops,
953 },
954 .shutdown = dra7xx_pcie_shutdown,
955};
956module_platform_driver(dra7xx_pcie_driver);
957
958MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
959MODULE_DESCRIPTION("PCIe controller driver for TI DRA7xx SoCs");
960MODULE_LICENSE("GPL v2");
946};
947
948static struct platform_driver dra7xx_pcie_driver = {
949 .probe = dra7xx_pcie_probe,
950 .driver = {
951 .name = "dra7-pcie",
952 .of_match_table = of_dra7xx_pcie_match,
953 .suppress_bind_attrs = true,
954 .pm = &dra7xx_pcie_pm_ops,
955 },
956 .shutdown = dra7xx_pcie_shutdown,
957};
958module_platform_driver(dra7xx_pcie_driver);
959
960MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
961MODULE_DESCRIPTION("PCIe controller driver for TI DRA7xx SoCs");
962MODULE_LICENSE("GPL v2");