pci-dra7xx.c (05909cd9a0c8811731b38697af13075e8954314f) pci-dra7xx.c (a0fd361db8e508b8ce71c284b5ae3961759a0b3b)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
4 *
5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Kishon Vijay Abraham I <kishon@ti.com>
8 */

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68
69#define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
70#define LTSSM_EN 0x1
71
72#define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
73#define LINK_UP BIT(16)
74#define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
75
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
4 *
5 * Copyright (C) 2013-2014 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Kishon Vijay Abraham I <kishon@ti.com>
8 */

--- 59 unchanged lines hidden (view full) ---

68
69#define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
70#define LTSSM_EN 0x1
71
72#define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
73#define LINK_UP BIT(16)
74#define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
75
76#define EXP_CAP_ID_OFFSET 0x70
77
78#define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124
79#define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128
80
81#define PCIECTRL_TI_CONF_MSI_XMT 0x012c
82#define MSI_REQ_GRANT BIT(0)
83#define MSI_VECTOR_SHIFT 7
84
85#define PCIE_1LANE_2LANE_SELECTION BIT(13)
86#define PCIE_B1C0_MODE_SEL BIT(2)
87#define PCIE_B0_B1_TSYNCEN BIT(0)
88
89struct dra7xx_pcie {
90 struct dw_pcie *pci;
91 void __iomem *base; /* DT ti_conf */
92 int phy_count; /* DT phy-names count */
93 struct phy **phy;
76#define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124
77#define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128
78
79#define PCIECTRL_TI_CONF_MSI_XMT 0x012c
80#define MSI_REQ_GRANT BIT(0)
81#define MSI_VECTOR_SHIFT 7
82
83#define PCIE_1LANE_2LANE_SELECTION BIT(13)
84#define PCIE_B1C0_MODE_SEL BIT(2)
85#define PCIE_B0_B1_TSYNCEN BIT(0)
86
87struct dra7xx_pcie {
88 struct dw_pcie *pci;
89 void __iomem *base; /* DT ti_conf */
90 int phy_count; /* DT phy-names count */
91 struct phy **phy;
94 int link_gen;
95 struct irq_domain *irq_domain;
96 enum dw_pcie_device_mode mode;
97};
98
99struct dra7xx_pcie_of_data {
100 enum dw_pcie_device_mode mode;
101 u32 b1co_mode_sel_mask;
102};

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137 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
138}
139
140static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
141{
142 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
143 struct device *dev = pci->dev;
144 u32 reg;
92 struct irq_domain *irq_domain;
93 enum dw_pcie_device_mode mode;
94};
95
96struct dra7xx_pcie_of_data {
97 enum dw_pcie_device_mode mode;
98 u32 b1co_mode_sel_mask;
99};

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134 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
135}
136
137static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
138{
139 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
140 struct device *dev = pci->dev;
141 u32 reg;
145 u32 exp_cap_off = EXP_CAP_ID_OFFSET;
146
147 if (dw_pcie_link_up(pci)) {
148 dev_err(dev, "link is already up\n");
149 return 0;
150 }
151
142
143 if (dw_pcie_link_up(pci)) {
144 dev_err(dev, "link is already up\n");
145 return 0;
146 }
147
152 if (dra7xx->link_gen == 1) {
153 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
154 4, &reg);
155 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
156 reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
157 reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
158 dw_pcie_write(pci->dbi_base + exp_cap_off +
159 PCI_EXP_LNKCAP, 4, reg);
160 }
161
162 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
163 2, &reg);
164 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
165 reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
166 reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
167 dw_pcie_write(pci->dbi_base + exp_cap_off +
168 PCI_EXP_LNKCTL2, 2, reg);
169 }
170 }
171
172 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
173 reg |= LTSSM_EN;
174 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
175
176 return 0;
177}
178
179static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)

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485 .irq_set_affinity = dra7xx_pcie_msi_set_affinity,
486 .irq_mask = dra7xx_pcie_bottom_mask,
487 .irq_unmask = dra7xx_pcie_bottom_unmask,
488};
489
490static int dra7xx_pcie_msi_host_init(struct pcie_port *pp)
491{
492 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
148 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
149 reg |= LTSSM_EN;
150 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
151
152 return 0;
153}
154
155static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)

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461 .irq_set_affinity = dra7xx_pcie_msi_set_affinity,
462 .irq_mask = dra7xx_pcie_bottom_mask,
463 .irq_unmask = dra7xx_pcie_bottom_unmask,
464};
465
466static int dra7xx_pcie_msi_host_init(struct pcie_port *pp)
467{
468 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
469 struct device *dev = pci->dev;
493 u32 ctrl, num_ctrls;
470 u32 ctrl, num_ctrls;
471 int ret;
494
495 pp->msi_irq_chip = &dra7xx_pci_msi_bottom_irq_chip;
496
497 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
498 /* Initialize IRQ Status array */
499 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
500 pp->irq_mask[ctrl] = ~0;
501 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
502 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
503 pp->irq_mask[ctrl]);
504 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
505 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
506 ~0);
507 }
508
472
473 pp->msi_irq_chip = &dra7xx_pci_msi_bottom_irq_chip;
474
475 num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
476 /* Initialize IRQ Status array */
477 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
478 pp->irq_mask[ctrl] = ~0;
479 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK +
480 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
481 pp->irq_mask[ctrl]);
482 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE +
483 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
484 ~0);
485 }
486
509 return dw_pcie_allocate_domains(pp);
487 ret = dw_pcie_allocate_domains(pp);
488 if (ret)
489 return ret;
490
491 pp->msi_data = dma_map_single_attrs(dev, &pp->msi_msg,
492 sizeof(pp->msi_msg),
493 DMA_FROM_DEVICE,
494 DMA_ATTR_SKIP_CPU_SYNC);
495 ret = dma_mapping_error(dev, pp->msi_data);
496 if (ret) {
497 dev_err(dev, "Failed to map MSI data\n");
498 pp->msi_data = 0;
499 dw_pcie_free_msi(pp);
500 }
501 return ret;
510}
511
512static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
513 .host_init = dra7xx_pcie_host_init,
514 .msi_host_init = dra7xx_pcie_msi_host_init,
515};
516
517static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)

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581 .get_features = dra7xx_pcie_get_features,
582};
583
584static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
585 struct platform_device *pdev)
586{
587 int ret;
588 struct dw_pcie_ep *ep;
502}
503
504static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
505 .host_init = dra7xx_pcie_host_init,
506 .msi_host_init = dra7xx_pcie_msi_host_init,
507};
508
509static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)

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573 .get_features = dra7xx_pcie_get_features,
574};
575
576static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
577 struct platform_device *pdev)
578{
579 int ret;
580 struct dw_pcie_ep *ep;
589 struct resource *res;
590 struct device *dev = &pdev->dev;
591 struct dw_pcie *pci = dra7xx->pci;
592
593 ep = &pci->ep;
594 ep->ops = &pcie_ep_ops;
595
596 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "ep_dbics");
597 if (IS_ERR(pci->dbi_base))
598 return PTR_ERR(pci->dbi_base);
599
600 pci->dbi_base2 =
601 devm_platform_ioremap_resource_byname(pdev, "ep_dbics2");
602 if (IS_ERR(pci->dbi_base2))
603 return PTR_ERR(pci->dbi_base2);
604
581 struct device *dev = &pdev->dev;
582 struct dw_pcie *pci = dra7xx->pci;
583
584 ep = &pci->ep;
585 ep->ops = &pcie_ep_ops;
586
587 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "ep_dbics");
588 if (IS_ERR(pci->dbi_base))
589 return PTR_ERR(pci->dbi_base);
590
591 pci->dbi_base2 =
592 devm_platform_ioremap_resource_byname(pdev, "ep_dbics2");
593 if (IS_ERR(pci->dbi_base2))
594 return PTR_ERR(pci->dbi_base2);
595
605 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
606 if (!res)
607 return -EINVAL;
608
609 ep->phys_base = res->start;
610 ep->addr_size = resource_size(res);
611
612 ret = dw_pcie_ep_init(ep);
613 if (ret) {
614 dev_err(dev, "failed to initialize endpoint\n");
615 return ret;
616 }
617
618 return 0;
619}

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932 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
933 goto err_gpio;
934 }
935
936 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
937 reg &= ~LTSSM_EN;
938 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
939
596 ret = dw_pcie_ep_init(ep);
597 if (ret) {
598 dev_err(dev, "failed to initialize endpoint\n");
599 return ret;
600 }
601
602 return 0;
603}

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916 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
917 goto err_gpio;
918 }
919
920 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
921 reg &= ~LTSSM_EN;
922 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
923
940 dra7xx->link_gen = of_pci_get_max_link_speed(np);
941 if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
942 dra7xx->link_gen = 2;
943
944 switch (mode) {
945 case DW_PCIE_RC_TYPE:
946 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
947 ret = -ENODEV;
948 goto err_gpio;
949 }
950
951 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,

--- 145 unchanged lines hidden --- 		924 switch (mode) {
925 case DW_PCIE_RC_TYPE:
926 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
927 ret = -ENODEV;
928 goto err_gpio;
929 }
930
931 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,

--- 145 unchanged lines hidden ---