admin-cmd.c (be602cde657ee43d23adbf309be6d700d0106dc9) admin-cmd.c (5a47c2080a7316f184107464e4f76737c0c05186)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * NVMe admin command implementation.
4 * Copyright (c) 2015-2016 HGST, a Western Digital Company.
5 */
6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7#include <linux/module.h>
8#include <linux/rculist.h>

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171 log->acs[nvme_admin_get_features] =
172 log->acs[nvme_admin_async_event] =
173 log->acs[nvme_admin_keep_alive] =
174 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP);
175
176 log->iocs[nvme_cmd_read] =
177 log->iocs[nvme_cmd_flush] =
178 log->iocs[nvme_cmd_dsm] =
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * NVMe admin command implementation.
4 * Copyright (c) 2015-2016 HGST, a Western Digital Company.
5 */
6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7#include <linux/module.h>
8#include <linux/rculist.h>

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171 log->acs[nvme_admin_get_features] =
172 log->acs[nvme_admin_async_event] =
173 log->acs[nvme_admin_keep_alive] =
174 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP);
175
176 log->iocs[nvme_cmd_read] =
177 log->iocs[nvme_cmd_flush] =
178 log->iocs[nvme_cmd_dsm] =
179 log->iocs[nvme_cmd_resv_acquire] =
180 log->iocs[nvme_cmd_resv_register] =
181 log->iocs[nvme_cmd_resv_release] =
182 log->iocs[nvme_cmd_resv_report] =
179 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP);
180 log->iocs[nvme_cmd_write] =
181 log->iocs[nvme_cmd_write_zeroes] =
182 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC);
183}
184
185static void nvmet_get_cmd_effects_zns(struct nvme_effects_log *log)
186{

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335 */
336 return nvmet_execute_get_log_page_noop(req);
337 case NVME_LOG_CHANGED_NS:
338 return nvmet_execute_get_log_changed_ns(req);
339 case NVME_LOG_CMD_EFFECTS:
340 return nvmet_execute_get_log_cmd_effects_ns(req);
341 case NVME_LOG_ANA:
342 return nvmet_execute_get_log_page_ana(req);
183 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP);
184 log->iocs[nvme_cmd_write] =
185 log->iocs[nvme_cmd_write_zeroes] =
186 cpu_to_le32(NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC);
187}
188
189static void nvmet_get_cmd_effects_zns(struct nvme_effects_log *log)
190{

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339 */
340 return nvmet_execute_get_log_page_noop(req);
341 case NVME_LOG_CHANGED_NS:
342 return nvmet_execute_get_log_changed_ns(req);
343 case NVME_LOG_CMD_EFFECTS:
344 return nvmet_execute_get_log_cmd_effects_ns(req);
345 case NVME_LOG_ANA:
346 return nvmet_execute_get_log_page_ana(req);
347 case NVME_LOG_RESERVATION:
348 return nvmet_execute_get_log_page_resv(req);
343 }
344 pr_debug("unhandled lid %d on qid %d\n",
345 req->cmd->get_log_page.lid, req->sq->qid);
346 req->error_loc = offsetof(struct nvme_get_log_page_command, lid);
347 nvmet_req_complete(req, NVME_SC_INVALID_FIELD | NVME_STATUS_DNR);
348}
349
350static void nvmet_execute_identify_ctrl(struct nvmet_req *req)

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428 id->cqes = (0x4 << 4) | 0x4;
429
430 /* no enforcement soft-limit for maxcmd - pick arbitrary high value */
431 id->maxcmd = cpu_to_le16(NVMET_MAX_CMD(ctrl));
432
433 id->nn = cpu_to_le32(NVMET_MAX_NAMESPACES);
434 id->mnan = cpu_to_le32(NVMET_MAX_NAMESPACES);
435 id->oncs = cpu_to_le16(NVME_CTRL_ONCS_DSM |
349 }
350 pr_debug("unhandled lid %d on qid %d\n",
351 req->cmd->get_log_page.lid, req->sq->qid);
352 req->error_loc = offsetof(struct nvme_get_log_page_command, lid);
353 nvmet_req_complete(req, NVME_SC_INVALID_FIELD | NVME_STATUS_DNR);
354}
355
356static void nvmet_execute_identify_ctrl(struct nvmet_req *req)

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434 id->cqes = (0x4 << 4) | 0x4;
435
436 /* no enforcement soft-limit for maxcmd - pick arbitrary high value */
437 id->maxcmd = cpu_to_le16(NVMET_MAX_CMD(ctrl));
438
439 id->nn = cpu_to_le32(NVMET_MAX_NAMESPACES);
440 id->mnan = cpu_to_le32(NVMET_MAX_NAMESPACES);
441 id->oncs = cpu_to_le16(NVME_CTRL_ONCS_DSM |
436 NVME_CTRL_ONCS_WRITE_ZEROES);
442 NVME_CTRL_ONCS_WRITE_ZEROES |
443 NVME_CTRL_ONCS_RESERVATIONS);
437
438 /* XXX: don't report vwc if the underlying device is write through */
439 id->vwc = NVME_CTRL_VWC_PRESENT;
440
441 /*
442 * We can't support atomic writes bigger than a LBA without support
443 * from the backend device.
444 */

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546
547 /*
548 * Our namespace might always be shared. Not just with other
549 * controllers, but also with any other user of the block device.
550 */
551 id->nmic = NVME_NS_NMIC_SHARED;
552 id->anagrpid = cpu_to_le32(req->ns->anagrpid);
553
444
445 /* XXX: don't report vwc if the underlying device is write through */
446 id->vwc = NVME_CTRL_VWC_PRESENT;
447
448 /*
449 * We can't support atomic writes bigger than a LBA without support
450 * from the backend device.
451 */

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553
554 /*
555 * Our namespace might always be shared. Not just with other
556 * controllers, but also with any other user of the block device.
557 */
558 id->nmic = NVME_NS_NMIC_SHARED;
559 id->anagrpid = cpu_to_le32(req->ns->anagrpid);
560
561 if (req->ns->pr.enable)
562 id->rescap = NVME_PR_SUPPORT_WRITE_EXCLUSIVE |
563 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS |
564 NVME_PR_SUPPORT_WRITE_EXCLUSIVE_REG_ONLY |
565 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS_REG_ONLY |
566 NVME_PR_SUPPORT_WRITE_EXCLUSIVE_ALL_REGS |
567 NVME_PR_SUPPORT_EXCLUSIVE_ACCESS_ALL_REGS |
568 NVME_PR_SUPPORT_IEKEY_VER_1_3_DEF;
569
554 memcpy(&id->nguid, &req->ns->nguid, sizeof(id->nguid));
555
556 id->lbaf[0].ds = req->ns->blksize_shift;
557
558 if (req->sq->ctrl->pi_support && nvmet_ns_has_pi(req->ns)) {
559 id->dpc = NVME_NS_DPC_PI_FIRST | NVME_NS_DPC_PI_LAST |
560 NVME_NS_DPC_PI_TYPE1 | NVME_NS_DPC_PI_TYPE2 |
561 NVME_NS_DPC_PI_TYPE3;

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856 status = nvmet_set_feat_async_event(req, NVMET_AEN_CFG_ALL);
857 break;
858 case NVME_FEAT_HOST_ID:
859 status = NVME_SC_CMD_SEQ_ERROR | NVME_STATUS_DNR;
860 break;
861 case NVME_FEAT_WRITE_PROTECT:
862 status = nvmet_set_feat_write_protect(req);
863 break;
570 memcpy(&id->nguid, &req->ns->nguid, sizeof(id->nguid));
571
572 id->lbaf[0].ds = req->ns->blksize_shift;
573
574 if (req->sq->ctrl->pi_support && nvmet_ns_has_pi(req->ns)) {
575 id->dpc = NVME_NS_DPC_PI_FIRST | NVME_NS_DPC_PI_LAST |
576 NVME_NS_DPC_PI_TYPE1 | NVME_NS_DPC_PI_TYPE2 |
577 NVME_NS_DPC_PI_TYPE3;

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872 status = nvmet_set_feat_async_event(req, NVMET_AEN_CFG_ALL);
873 break;
874 case NVME_FEAT_HOST_ID:
875 status = NVME_SC_CMD_SEQ_ERROR | NVME_STATUS_DNR;
876 break;
877 case NVME_FEAT_WRITE_PROTECT:
878 status = nvmet_set_feat_write_protect(req);
879 break;
880 case NVME_FEAT_RESV_MASK:
881 status = nvmet_set_feat_resv_notif_mask(req, cdw11);
882 break;
864 default:
865 req->error_loc = offsetof(struct nvme_common_command, cdw10);
866 status = NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
867 break;
868 }
869
870 nvmet_req_complete(req, status);
871}

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954 }
955
956 status = nvmet_copy_to_sgl(req, 0, &req->sq->ctrl->hostid,
957 sizeof(req->sq->ctrl->hostid));
958 break;
959 case NVME_FEAT_WRITE_PROTECT:
960 status = nvmet_get_feat_write_protect(req);
961 break;
883 default:
884 req->error_loc = offsetof(struct nvme_common_command, cdw10);
885 status = NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
886 break;
887 }
888
889 nvmet_req_complete(req, status);
890}

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973 }
974
975 status = nvmet_copy_to_sgl(req, 0, &req->sq->ctrl->hostid,
976 sizeof(req->sq->ctrl->hostid));
977 break;
978 case NVME_FEAT_WRITE_PROTECT:
979 status = nvmet_get_feat_write_protect(req);
980 break;
981 case NVME_FEAT_RESV_MASK:
982 status = nvmet_get_feat_resv_notif_mask(req);
983 break;
962 default:
963 req->error_loc =
964 offsetof(struct nvme_common_command, cdw10);
965 status = NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
966 break;
967 }
968
969 nvmet_req_complete(req, status);

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985 req->error_loc =
986 offsetof(struct nvme_common_command, cdw10);
987 status = NVME_SC_INVALID_FIELD | NVME_STATUS_DNR;
988 break;
989 }
990
991 nvmet_req_complete(req, status);

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