mac.h (0326074ff4652329f2a1a9c8685104576bd8d131) mac.h (732dd91db3d3a1b7a767598549ffed358c9fbb89)
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#ifndef __RTW89_MAC_H__
6#define __RTW89_MAC_H__
7
8#include "core.h"

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240#define BA_CAM_BASE_ADDR 0x18854000
241#define BCN_IE_CAM0_BASE_ADDR 0x18855000
242#define SHARED_BUF_BASE_ADDR 0x18700000
243#define DMAC_TBL_BASE_ADDR 0x18800000
244#define SHCUT_MACHDR_BASE_ADDR 0x18800800
245#define BCN_IE_CAM1_BASE_ADDR 0x188A0000
246#define TXD_FIFO_0_BASE_ADDR 0x18856200
247#define TXD_FIFO_1_BASE_ADDR 0x188A1080
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#ifndef __RTW89_MAC_H__
6#define __RTW89_MAC_H__
7
8#include "core.h"

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240#define BA_CAM_BASE_ADDR 0x18854000
241#define BCN_IE_CAM0_BASE_ADDR 0x18855000
242#define SHARED_BUF_BASE_ADDR 0x18700000
243#define DMAC_TBL_BASE_ADDR 0x18800000
244#define SHCUT_MACHDR_BASE_ADDR 0x18800800
245#define BCN_IE_CAM1_BASE_ADDR 0x188A0000
246#define TXD_FIFO_0_BASE_ADDR 0x18856200
247#define TXD_FIFO_1_BASE_ADDR 0x188A1080
248#define TXD_FIFO_0_BASE_ADDR_V1 0x18856400 /* for 8852C */
249#define TXD_FIFO_1_BASE_ADDR_V1 0x188A1080 /* for 8852C */
248#define TXDATA_FIFO_0_BASE_ADDR 0x18856000
249#define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
250#define CPU_LOCAL_BASE_ADDR 0x18003000
251
252#define CCTL_INFO_SIZE 32
253
254enum rtw89_mac_mem_sel {
255 RTW89_MAC_MEM_AXIDMA,

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266 RTW89_MAC_MEM_BCN_IE_CAM0,
267 RTW89_MAC_MEM_BCN_IE_CAM1,
268 RTW89_MAC_MEM_TXD_FIFO_0,
269 RTW89_MAC_MEM_TXD_FIFO_1,
270 RTW89_MAC_MEM_TXDATA_FIFO_0,
271 RTW89_MAC_MEM_TXDATA_FIFO_1,
272 RTW89_MAC_MEM_CPU_LOCAL,
273 RTW89_MAC_MEM_BSSID_CAM,
250#define TXDATA_FIFO_0_BASE_ADDR 0x18856000
251#define TXDATA_FIFO_1_BASE_ADDR 0x188A1000
252#define CPU_LOCAL_BASE_ADDR 0x18003000
253
254#define CCTL_INFO_SIZE 32
255
256enum rtw89_mac_mem_sel {
257 RTW89_MAC_MEM_AXIDMA,

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268 RTW89_MAC_MEM_BCN_IE_CAM0,
269 RTW89_MAC_MEM_BCN_IE_CAM1,
270 RTW89_MAC_MEM_TXD_FIFO_0,
271 RTW89_MAC_MEM_TXD_FIFO_1,
272 RTW89_MAC_MEM_TXDATA_FIFO_0,
273 RTW89_MAC_MEM_TXDATA_FIFO_1,
274 RTW89_MAC_MEM_CPU_LOCAL,
275 RTW89_MAC_MEM_BSSID_CAM,
276 RTW89_MAC_MEM_TXD_FIFO_0_V1,
277 RTW89_MAC_MEM_TXD_FIFO_1_V1,
274
275 /* keep last */
276 RTW89_MAC_MEM_NUM,
277};
278
279extern const u32 rtw89_mac_mem_base_addrs[];
280
281enum rtw89_rpwm_req_pwr_state {

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279 /* keep last */
280 RTW89_MAC_MEM_NUM,
281};
282
283extern const u32 rtw89_mac_mem_base_addrs[];
284
285enum rtw89_rpwm_req_pwr_state {

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