tx.h (14e77332e74603efab8347c89d3cda447c3b97c9) tx.h (a82dfd33d1237f6c0fb8a7077022189d1fc7ec98)
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5#ifndef __RTW_TX_H_
6#define __RTW_TX_H_
7
8#define RTK_TX_MAX_AGG_NUM_MASK 0x1f

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66#define SET_TX_DESC_EN_HWSEQ(txdesc, value) \
67 le32p_replace_bits((__le32 *)(txdesc) + 0x08, value, BIT(15))
68#define SET_TX_DESC_HW_SSN_SEL(txdesc, value) \
69 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, GENMASK(7, 6))
70#define SET_TX_DESC_NAVUSEHDR(txdesc, value) \
71 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(15))
72#define SET_TX_DESC_BT_NULL(txdesc, value) \
73 le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(23))
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5#ifndef __RTW_TX_H_
6#define __RTW_TX_H_
7
8#define RTK_TX_MAX_AGG_NUM_MASK 0x1f

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66#define SET_TX_DESC_EN_HWSEQ(txdesc, value) \
67 le32p_replace_bits((__le32 *)(txdesc) + 0x08, value, BIT(15))
68#define SET_TX_DESC_HW_SSN_SEL(txdesc, value) \
69 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, GENMASK(7, 6))
70#define SET_TX_DESC_NAVUSEHDR(txdesc, value) \
71 le32p_replace_bits((__le32 *)(txdesc) + 0x03, value, BIT(15))
72#define SET_TX_DESC_BT_NULL(txdesc, value) \
73 le32p_replace_bits((__le32 *)(txdesc) + 0x02, value, BIT(23))
74#define SET_TX_DESC_TXDESC_CHECKSUM(txdesc, value) \
75 le32p_replace_bits((__le32 *)(txdesc) + 0x07, value, GENMASK(15, 0))
76#define SET_TX_DESC_DMA_TXAGG_NUM(txdesc, value) \
77 le32p_replace_bits((__le32 *)(txdesc) + 0x07, value, GENMASK(31, 24))
78#define GET_TX_DESC_PKT_OFFSET(txdesc) \
79 le32_get_bits(*((__le32 *)(txdesc) + 0x01), GENMASK(28, 24))
80#define GET_TX_DESC_QSEL(txdesc) \
81 le32_get_bits(*((__le32 *)(txdesc) + 0x01), GENMASK(12, 8))
74
75enum rtw_tx_desc_queue_select {
76 TX_DESC_QSEL_TID0 = 0,
77 TX_DESC_QSEL_TID1 = 1,
78 TX_DESC_QSEL_TID2 = 2,
79 TX_DESC_QSEL_TID3 = 3,
80 TX_DESC_QSEL_TID4 = 4,
81 TX_DESC_QSEL_TID5 = 5,

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118rtw_tx_write_data_rsvd_page_get(struct rtw_dev *rtwdev,
119 struct rtw_tx_pkt_info *pkt_info,
120 u8 *buf, u32 size);
121struct sk_buff *
122rtw_tx_write_data_h2c_get(struct rtw_dev *rtwdev,
123 struct rtw_tx_pkt_info *pkt_info,
124 u8 *buf, u32 size);
125
82
83enum rtw_tx_desc_queue_select {
84 TX_DESC_QSEL_TID0 = 0,
85 TX_DESC_QSEL_TID1 = 1,
86 TX_DESC_QSEL_TID2 = 2,
87 TX_DESC_QSEL_TID3 = 3,
88 TX_DESC_QSEL_TID4 = 4,
89 TX_DESC_QSEL_TID5 = 5,

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126rtw_tx_write_data_rsvd_page_get(struct rtw_dev *rtwdev,
127 struct rtw_tx_pkt_info *pkt_info,
128 u8 *buf, u32 size);
129struct sk_buff *
130rtw_tx_write_data_h2c_get(struct rtw_dev *rtwdev,
131 struct rtw_tx_pkt_info *pkt_info,
132 u8 *buf, u32 size);
133
134static inline
135void fill_txdesc_checksum_common(u8 *txdesc, size_t words)
136{
137 __le16 chksum = 0;
138 __le16 *data = (__le16 *)(txdesc);
139
140 SET_TX_DESC_TXDESC_CHECKSUM(txdesc, 0x0000);
141
142 while (words--)
143 chksum ^= *data++;
144
145 SET_TX_DESC_TXDESC_CHECKSUM(txdesc, __le16_to_cpu(chksum));
146}
147
148static inline void rtw_tx_fill_txdesc_checksum(struct rtw_dev *rtwdev,
149 struct rtw_tx_pkt_info *pkt_info,
150 u8 *txdesc)
151{
152 const struct rtw_chip_info *chip = rtwdev->chip;
153
154 chip->ops->fill_txdesc_checksum(rtwdev, pkt_info, txdesc);
155}
156
126#endif
157#endif