rtw8821c.c (29583dfcd2dd72c766422bd05c16f06c6b1fb356) rtw8821c.c (aff5ffd718de23cb8603f2e229204670e2644334)
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5#include "main.h"
6#include "coex.h"
7#include "fw.h"
8#include "tx.h"

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21 -20, -24, -28, -31, -34, -37, -40, -44};
22
23static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse,
24 struct rtw8821c_efuse *map)
25{
26 ether_addr_copy(efuse->addr, map->e.mac_addr);
27}
28
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2018-2019 Realtek Corporation
3 */
4
5#include "main.h"
6#include "coex.h"
7#include "fw.h"
8#include "tx.h"

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21 -20, -24, -28, -31, -34, -37, -40, -44};
22
23static void rtw8821ce_efuse_parsing(struct rtw_efuse *efuse,
24 struct rtw8821c_efuse *map)
25{
26 ether_addr_copy(efuse->addr, map->e.mac_addr);
27}
28
29static void rtw8821cu_efuse_parsing(struct rtw_efuse *efuse,
30 struct rtw8821c_efuse *map)
31{
32 ether_addr_copy(efuse->addr, map->u.mac_addr);
33}
34
29enum rtw8821ce_rf_set {
30 SWITCH_TO_BTG,
31 SWITCH_TO_WLG,
32 SWITCH_TO_WLA,
33 SWITCH_TO_BT,
34};
35
36static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)

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63
64 if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4)
65 efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g;
66
67 switch (rtw_hci_type(rtwdev)) {
68 case RTW_HCI_TYPE_PCIE:
69 rtw8821ce_efuse_parsing(efuse, map);
70 break;
35enum rtw8821ce_rf_set {
36 SWITCH_TO_BTG,
37 SWITCH_TO_WLG,
38 SWITCH_TO_WLA,
39 SWITCH_TO_BT,
40};
41
42static int rtw8821c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)

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69
70 if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4)
71 efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g;
72
73 switch (rtw_hci_type(rtwdev)) {
74 case RTW_HCI_TYPE_PCIE:
75 rtw8821ce_efuse_parsing(efuse, map);
76 break;
77 case RTW_HCI_TYPE_USB:
78 rtw8821cu_efuse_parsing(efuse, map);
79 break;
71 default:
72 /* unsupported now */
73 return -ENOTSUPP;
74 }
75
76 return 0;
77}
78

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1143 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
1144
1145 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
1146 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);
1147 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,
1148 dm_info->cck_pd_default + new_lvl * 2);
1149}
1150
80 default:
81 /* unsupported now */
82 return -ENOTSUPP;
83 }
84
85 return 0;
86}
87

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1152 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
1153
1154 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
1155 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]);
1156 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000,
1157 dm_info->cck_pd_default + new_lvl * 2);
1158}
1159
1160static void rtw8821c_fill_txdesc_checksum(struct rtw_dev *rtwdev,
1161 struct rtw_tx_pkt_info *pkt_info,
1162 u8 *txdesc)
1163{
1164 fill_txdesc_checksum_common(txdesc, 16);
1165}
1166
1151static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = {
1152 {0x0086,
1153 RTW_PWR_CUT_ALL_MSK,
1154 RTW_PWR_INTF_SDIO_MSK,
1155 RTW_PWR_ADDR_SDIO,
1156 RTW_PWR_CMD_WRITE, BIT(0), 0},
1157 {0x0086,
1158 RTW_PWR_CUT_ALL_MSK,

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1516 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8821c),
1517};
1518
1519static const struct rtw_rfe_def rtw8821c_rfe_defs[] = {
1520 [0] = RTW_DEF_RFE(8821c, 0, 0),
1521 [2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
1522 [4] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
1523 [6] = RTW_DEF_RFE(8821c, 0, 0),
1167static struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8821c[] = {
1168 {0x0086,
1169 RTW_PWR_CUT_ALL_MSK,
1170 RTW_PWR_INTF_SDIO_MSK,
1171 RTW_PWR_ADDR_SDIO,
1172 RTW_PWR_CMD_WRITE, BIT(0), 0},
1173 {0x0086,
1174 RTW_PWR_CUT_ALL_MSK,

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1532 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8821c),
1533};
1534
1535static const struct rtw_rfe_def rtw8821c_rfe_defs[] = {
1536 [0] = RTW_DEF_RFE(8821c, 0, 0),
1537 [2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
1538 [4] = RTW_DEF_RFE_EXT(8821c, 0, 0, 2),
1539 [6] = RTW_DEF_RFE(8821c, 0, 0),
1540 [34] = RTW_DEF_RFE(8821c, 0, 0),
1524};
1525
1526static struct rtw_hw_reg rtw8821c_dig[] = {
1527 [0] = { .addr = 0xc50, .mask = 0x7f },
1528};
1529
1530static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = {
1531 .ctrl = LTECOEX_ACCESS_CTRL,

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1590 .cfg_ldo25 = rtw8821c_cfg_ldo25,
1591 .false_alarm_statistics = rtw8821c_false_alarm_statistics,
1592 .phy_calibration = rtw8821c_phy_calibration,
1593 .cck_pd_set = rtw8821c_phy_cck_pd_set,
1594 .pwr_track = rtw8821c_pwr_track,
1595 .config_bfee = rtw8821c_bf_config_bfee,
1596 .set_gid_table = rtw_bf_set_gid_table,
1597 .cfg_csi_rate = rtw_bf_cfg_csi_rate,
1541};
1542
1543static struct rtw_hw_reg rtw8821c_dig[] = {
1544 [0] = { .addr = 0xc50, .mask = 0x7f },
1545};
1546
1547static const struct rtw_ltecoex_addr rtw8821c_ltecoex_addr = {
1548 .ctrl = LTECOEX_ACCESS_CTRL,

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1607 .cfg_ldo25 = rtw8821c_cfg_ldo25,
1608 .false_alarm_statistics = rtw8821c_false_alarm_statistics,
1609 .phy_calibration = rtw8821c_phy_calibration,
1610 .cck_pd_set = rtw8821c_phy_cck_pd_set,
1611 .pwr_track = rtw8821c_pwr_track,
1612 .config_bfee = rtw8821c_bf_config_bfee,
1613 .set_gid_table = rtw_bf_set_gid_table,
1614 .cfg_csi_rate = rtw_bf_cfg_csi_rate,
1615 .fill_txdesc_checksum = rtw8821c_fill_txdesc_checksum,
1598
1599 .coex_set_init = rtw8821c_coex_cfg_init,
1600 .coex_set_ant_switch = rtw8821c_coex_cfg_ant_switch,
1601 .coex_set_gnt_fix = rtw8821c_coex_cfg_gnt_fix,
1602 .coex_set_gnt_debug = rtw8821c_coex_cfg_gnt_debug,
1603 .coex_set_rfe_type = rtw8821c_coex_cfg_rfe_type,
1604 .coex_set_wl_tx_power = rtw8821c_coex_cfg_wl_tx_power,
1605 .coex_set_wl_rx_gain = rtw8821c_coex_cfg_wl_rx_gain,

--- 363 unchanged lines hidden --- 		1616
1617 .coex_set_init = rtw8821c_coex_cfg_init,
1618 .coex_set_ant_switch = rtw8821c_coex_cfg_ant_switch,
1619 .coex_set_gnt_fix = rtw8821c_coex_cfg_gnt_fix,
1620 .coex_set_gnt_debug = rtw8821c_coex_cfg_gnt_debug,
1621 .coex_set_rfe_type = rtw8821c_coex_cfg_rfe_type,
1622 .coex_set_wl_tx_power = rtw8821c_coex_cfg_wl_tx_power,
1623 .coex_set_wl_rx_gain = rtw8821c_coex_cfg_wl_rx_gain,

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