| pwrseq.h (e5451c8f8330e03ad3cfa16048b4daf961af434f) | pwrseq.h (692f5deccdae665925cd9542d460fe4771835be5) |
|---|---|
| 1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2014 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * --- 190 unchanged lines hidden (view full) --- 199 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 200 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \ 201 /*wait power state to suspend*/ \ 202 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 203 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ 204 /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ 205 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 206 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ | 1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2014 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * --- 190 unchanged lines hidden (view full) --- 199 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 200 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \ 201 /*wait power state to suspend*/ \ 202 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 203 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ 204 /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ 205 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 206 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ |
| 207 /*0x04[12:11] = 2b'01enable WL suspend*/ \ | 207 /*0x04[12:11] = 2b'00 disable WL suspend*/ \ |
| 208 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 209 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, 210 211#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS \ 212 /* format */ \ 213 /* comments here */ \ 214 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\ 215 /*0x07=0x20 , SOP option to disable BG/MB*/ \ --- 30 unchanged lines hidden (view full) --- 246 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 247 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \ 248 /*wait power state to suspend*/ \ 249 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 250 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ 251 /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ 252 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \ 253 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ | 208 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 209 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, 210 211#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS \ 212 /* format */ \ 213 /* comments here */ \ 214 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\ 215 /*0x07=0x20 , SOP option to disable BG/MB*/ \ --- 30 unchanged lines hidden (view full) --- 246 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 247 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \ 248 /*wait power state to suspend*/ \ 249 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 250 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \ 251 /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \ 252 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \ 253 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \ |
| 254 /*0x04[12:11] = 2b'01enable WL suspend*/ \ | 254 /*0x04[12:11] = 2b'00 disable WL suspend*/ \ |
| 255 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 256 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \ 257 /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ 258 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 259 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ 260 /*PCIe DMA start*/ \ 261 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 262 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, --- 161 unchanged lines hidden --- | 255 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \ 256 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \ 257 /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \ 258 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \ 259 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \ 260 /*PCIe DMA start*/ \ 261 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \ 262 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, --- 161 unchanged lines hidden --- |