phy.c (5bd4f692e0eba585674c58f68b8ff62c21468a2f) phy.c (b83faeda028bf361db9c796396e710d5fb1337b0)
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4#include "../wifi.h"
5#include "../pci.h"
6#include "../ps.h"
7#include "../core.h"
8#include "reg.h"

--- 470 unchanged lines hidden (view full) ---

479
480 /*RX AFE control 1 */
481 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
482 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
483 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
484 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
485
486 /* Tx AFE control 1 */
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4#include "../wifi.h"
5#include "../pci.h"
6#include "../ps.h"
7#include "../core.h"
8#include "reg.h"

--- 470 unchanged lines hidden (view full) ---

479
480 /*RX AFE control 1 */
481 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
482 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
483 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
484 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
485
486 /* Tx AFE control 1 */
487 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATxIQIMBALANCE;
488 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTxIQIMBALANCE;
489 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTxIQIMBALANCE;
490 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTxIQIMBALANCE;
487 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
488 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
489 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
490 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
491
492 /* Tx AFE control 2 */
491
492 /* Tx AFE control 2 */
493 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATxAFE;
494 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTxAFE;
495 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTxAFE;
496 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE;
493 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
494 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
495 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
496 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
497
498 /* Tranceiver LSSI Readback SI mode */
499 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
500 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
501 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
502 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
503
504 /* Tranceiver LSSI Readback PI mode */

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737 regval | BIT(13) | BIT(0) | BIT(1));
738 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
739 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
740 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */
741 value = rtl_read_byte(rtlpriv, REG_RF_CTRL);
742 rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
743 RF_SDMRSTB);
744 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
497
498 /* Tranceiver LSSI Readback SI mode */
499 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
500 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
501 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
502 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
503
504 /* Tranceiver LSSI Readback PI mode */

--- 232 unchanged lines hidden (view full) ---

737 regval | BIT(13) | BIT(0) | BIT(1));
738 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
739 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
740 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */
741 value = rtl_read_byte(rtlpriv, REG_RF_CTRL);
742 rtl_write_byte(rtlpriv, REG_RF_CTRL, value | RF_EN | RF_RSTB |
743 RF_SDMRSTB);
744 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
745 FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
745 FEN_DIO_PCIE | FEN_BB_GLB_RSTN | FEN_BBRSTB);
746 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
747 if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
748 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
749 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
750 }
751
752 return _rtl92d_phy_bb_config(hw);
753}

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1453{
1454 struct rtl_priv *rtlpriv = rtl_priv(hw);
1455 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1456 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1457 u32 regeac, rege94, rege9c, regea4;
1458 u8 result = 0;
1459 u8 i;
1460 u8 retrycount = 2;
746 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
747 if (!(IS_92D_SINGLEPHY(rtlpriv->rtlhal.version))) {
748 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
749 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
750 }
751
752 return _rtl92d_phy_bb_config(hw);
753}

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1453{
1454 struct rtl_priv *rtlpriv = rtl_priv(hw);
1455 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1456 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1457 u32 regeac, rege94, rege9c, regea4;
1458 u8 result = 0;
1459 u8 i;
1460 u8 retrycount = 2;
1461 u32 TxOKBit = BIT(28), RxOKBit = BIT(27);
1461 u32 TXOKBIT = BIT(28), RXOKBIT = BIT(27);
1462
1463 if (rtlhal->interfaceindex == 1) { /* PHY1 */
1462
1463 if (rtlhal->interfaceindex == 1) { /* PHY1 */
1464 TxOKBit = BIT(31);
1465 RxOKBit = BIT(30);
1464 TXOKBIT = BIT(31);
1465 RXOKBIT = BIT(30);
1466 }
1467 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n");
1468 /* path-A IQK setting */
1469 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1470 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1471 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1472 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307);
1473 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960);

--- 25 unchanged lines hidden (view full) ---

1499 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1500 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1501 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1502 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
1503 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1504 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
1505 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1506 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
1466 }
1467 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path A IQK!\n");
1468 /* path-A IQK setting */
1469 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path-A IQK setting!\n");
1470 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f);
1471 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f);
1472 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307);
1473 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960);

--- 25 unchanged lines hidden (view full) ---

1499 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1500 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac);
1501 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1502 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94);
1503 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1504 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c);
1505 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1506 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4);
1507 if (!(regeac & TxOKBit) &&
1507 if (!(regeac & TXOKBIT) &&
1508 (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1509 result |= 0x01;
1510 } else { /* if Tx not OK, ignore Rx */
1511 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1512 "Path A Tx IQK fail!!\n");
1513 continue;
1514 }
1515
1516 /* if Tx is OK, check whether Rx is OK */
1508 (((rege94 & 0x03FF0000) >> 16) != 0x142)) {
1509 result |= 0x01;
1510 } else { /* if Tx not OK, ignore Rx */
1511 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1512 "Path A Tx IQK fail!!\n");
1513 continue;
1514 }
1515
1516 /* if Tx is OK, check whether Rx is OK */
1517 if (!(regeac & RxOKBit) &&
1517 if (!(regeac & RXOKBIT) &&
1518 (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1519 result |= 0x02;
1520 break;
1521 } else {
1522 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1523 "Path A Rx IQK fail!!\n");
1524 }
1525 }

--- 612 unchanged lines hidden (view full) ---

2138 bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
2139 rtlhal->macphymode == DUALMAC_DUALPHY;
2140
2141 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2142 "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed");
2143 if (final_candidate == 0xFF) {
2144 return;
2145 } else if (iqk_ok) {
1518 (((regea4 & 0x03FF0000) >> 16) != 0x132)) {
1519 result |= 0x02;
1520 break;
1521 } else {
1522 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1523 "Path A Rx IQK fail!!\n");
1524 }
1525 }

--- 612 unchanged lines hidden (view full) ---

2138 bool is2t = IS_92D_SINGLEPHY(rtlhal->version) ||
2139 rtlhal->macphymode == DUALMAC_DUALPHY;
2140
2141 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2142 "Path A IQ Calibration %s !\n", iqk_ok ? "Success" : "Failed");
2143 if (final_candidate == 0xFF) {
2144 return;
2145 } else if (iqk_ok) {
2146 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2146 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2147 MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */
2148 val_x = result[final_candidate][0];
2149 if ((val_x & 0x00000200) != 0)
2150 val_x = val_x | 0xFFFFFC00;
2151 tx0_a = (val_x * oldval_0) >> 8;
2152 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2153 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n",
2154 val_x, tx0_a, oldval_0);
2147 MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */
2148 val_x = result[final_candidate][0];
2149 if ((val_x & 0x00000200) != 0)
2150 val_x = val_x | 0xFFFFFC00;
2151 tx0_a = (val_x * oldval_0) >> 8;
2152 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2153 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n",
2154 val_x, tx0_a, oldval_0);
2155 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x3FF, tx0_a);
2155 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
2156 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2157 ((val_x * oldval_0 >> 7) & 0x1));
2158 val_y = result[final_candidate][1];
2159 if ((val_y & 0x00000200) != 0)
2160 val_y = val_y | 0xFFFFFC00;
2161 /* path B IQK result + 3 */
2162 if (rtlhal->interfaceindex == 1 &&
2163 rtlhal->current_bandtype == BAND_ON_5G)
2164 val_y += 3;
2165 tx0_c = (val_y * oldval_0) >> 8;
2166 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2167 "Y = 0x%lx, tx0_c = 0x%lx\n",
2168 val_y, tx0_c);
2156 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(24),
2157 ((val_x * oldval_0 >> 7) & 0x1));
2158 val_y = result[final_candidate][1];
2159 if ((val_y & 0x00000200) != 0)
2160 val_y = val_y | 0xFFFFFC00;
2161 /* path B IQK result + 3 */
2162 if (rtlhal->interfaceindex == 1 &&
2163 rtlhal->current_bandtype == BAND_ON_5G)
2164 val_y += 3;
2165 tx0_c = (val_y * oldval_0) >> 8;
2166 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2167 "Y = 0x%lx, tx0_c = 0x%lx\n",
2168 val_y, tx0_c);
2169 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000,
2169 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
2170 ((tx0_c & 0x3C0) >> 6));
2170 ((tx0_c & 0x3C0) >> 6));
2171 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, 0x003F0000,
2171 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
2172 (tx0_c & 0x3F));
2173 if (is2t)
2174 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2175 ((val_y * oldval_0 >> 7) & 0x1));
2176 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
2172 (tx0_c & 0x3F));
2173 if (is2t)
2174 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(26),
2175 ((val_y * oldval_0 >> 7) & 0x1));
2176 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n",
2177 rtl_get_bbreg(hw, ROFDM0_XATxIQIMBALANCE,
2177 rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
2178 MASKDWORD));
2179 if (txonly) {
2180 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n");
2181 return;
2182 }
2183 reg = result[final_candidate][2];
2184 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2185 reg = result[final_candidate][3] & 0x3F;

--- 11 unchanged lines hidden (view full) ---

2197 u32 oldval_1, val_x, tx1_a, reg;
2198 long val_y, tx1_c;
2199
2200 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n",
2201 iqk_ok ? "Success" : "Failed");
2202 if (final_candidate == 0xFF) {
2203 return;
2204 } else if (iqk_ok) {
2178 MASKDWORD));
2179 if (txonly) {
2180 RTPRINT(rtlpriv, FINIT, INIT_IQK, "only Tx OK\n");
2181 return;
2182 }
2183 reg = result[final_candidate][2];
2184 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
2185 reg = result[final_candidate][3] & 0x3F;

--- 11 unchanged lines hidden (view full) ---

2197 u32 oldval_1, val_x, tx1_a, reg;
2198 long val_y, tx1_c;
2199
2200 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Path B IQ Calibration %s !\n",
2201 iqk_ok ? "Success" : "Failed");
2202 if (final_candidate == 0xFF) {
2203 return;
2204 } else if (iqk_ok) {
2205 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTxIQIMBALANCE,
2205 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
2206 MASKDWORD) >> 22) & 0x3FF;
2207 val_x = result[final_candidate][4];
2208 if ((val_x & 0x00000200) != 0)
2209 val_x = val_x | 0xFFFFFC00;
2210 tx1_a = (val_x * oldval_1) >> 8;
2211 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n",
2212 val_x, tx1_a);
2206 MASKDWORD) >> 22) & 0x3FF;
2207 val_x = result[final_candidate][4];
2208 if ((val_x & 0x00000200) != 0)
2209 val_x = val_x | 0xFFFFFC00;
2210 tx1_a = (val_x * oldval_1) >> 8;
2211 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n",
2212 val_x, tx1_a);
2213 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x3FF, tx1_a);
2213 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
2214 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2215 ((val_x * oldval_1 >> 7) & 0x1));
2216 val_y = result[final_candidate][5];
2217 if ((val_y & 0x00000200) != 0)
2218 val_y = val_y | 0xFFFFFC00;
2219 if (rtlhal->current_bandtype == BAND_ON_5G)
2220 val_y += 3;
2221 tx1_c = (val_y * oldval_1) >> 8;
2222 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n",
2223 val_y, tx1_c);
2214 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(28),
2215 ((val_x * oldval_1 >> 7) & 0x1));
2216 val_y = result[final_candidate][5];
2217 if ((val_y & 0x00000200) != 0)
2218 val_y = val_y | 0xFFFFFC00;
2219 if (rtlhal->current_bandtype == BAND_ON_5G)
2220 val_y += 3;
2221 tx1_c = (val_y * oldval_1) >> 8;
2222 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n",
2223 val_y, tx1_c);
2224 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000,
2224 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
2225 ((tx1_c & 0x3C0) >> 6));
2225 ((tx1_c & 0x3C0) >> 6));
2226 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, 0x003F0000,
2226 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
2227 (tx1_c & 0x3F));
2228 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
2229 ((val_y * oldval_1 >> 7) & 0x1));
2230 if (txonly)
2231 return;
2232 reg = result[final_candidate][6];
2233 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2234 reg = result[final_candidate][7] & 0x3F;

--- 824 unchanged lines hidden (view full) ---

3059
3060 if (rfpwr_state == ppsc->rfpwr_state)
3061 return false;
3062 switch (rfpwr_state) {
3063 case ERFON:
3064 if ((ppsc->rfpwr_state == ERFOFF) &&
3065 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3066 bool rtstatus;
2227 (tx1_c & 0x3F));
2228 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30),
2229 ((val_y * oldval_1 >> 7) & 0x1));
2230 if (txonly)
2231 return;
2232 reg = result[final_candidate][6];
2233 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
2234 reg = result[final_candidate][7] & 0x3F;

--- 824 unchanged lines hidden (view full) ---

3059
3060 if (rfpwr_state == ppsc->rfpwr_state)
3061 return false;
3062 switch (rfpwr_state) {
3063 case ERFON:
3064 if ((ppsc->rfpwr_state == ERFOFF) &&
3065 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
3066 bool rtstatus;
3067 u32 InitializeCount = 0;
3067 u32 initializecount = 0;
3068 do {
3068 do {
3069 InitializeCount++;
3069 initializecount++;
3070 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3071 "IPS Set eRf nic enable\n");
3072 rtstatus = rtl_ps_enable_nic(hw);
3070 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3071 "IPS Set eRf nic enable\n");
3072 rtstatus = rtl_ps_enable_nic(hw);
3073 } while (!rtstatus && (InitializeCount < 10));
3073 } while (!rtstatus && (initializecount < 10));
3074
3075 RT_CLEAR_PS_LEVEL(ppsc,
3076 RT_RF_OFF_LEVL_HALT_NIC);
3077 } else {
3078 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3079 "awake, sleeped:%d ms state_inap:%x\n",
3080 jiffies_to_msecs(jiffies -
3081 ppsc->last_sleep_jiffies),

--- 278 unchanged lines hidden (view full) ---

3360 }
3361 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */
3362 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
3363 /* fc_area 0xd2c */
3364 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
3365 /* 5G LAN ON */
3366 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3367 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3074
3075 RT_CLEAR_PS_LEVEL(ppsc,
3076 RT_RF_OFF_LEVL_HALT_NIC);
3077 } else {
3078 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
3079 "awake, sleeped:%d ms state_inap:%x\n",
3080 jiffies_to_msecs(jiffies -
3081 ppsc->last_sleep_jiffies),

--- 278 unchanged lines hidden (view full) ---

3360 }
3361 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */
3362 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
3363 /* fc_area 0xd2c */
3364 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
3365 /* 5G LAN ON */
3366 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
3367 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
3368 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3368 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3369 0x40000100);
3369 0x40000100);
3370 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3370 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3371 0x40000100);
3372 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3373 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3374 BIT(10) | BIT(6) | BIT(5),
3375 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3376 (rtlefuse->eeprom_c9 & BIT(1)) |
3377 ((rtlefuse->eeprom_cc & BIT(1)) << 4));
3378 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,

--- 37 unchanged lines hidden (view full) ---

3416 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */
3417 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
3418 /* fc_area */
3419 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
3420 /* 5G LAN ON */
3421 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3422 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */
3423 if (rtlefuse->internal_pa_5g[0])
3371 0x40000100);
3372 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3373 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3374 BIT(10) | BIT(6) | BIT(5),
3375 ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
3376 (rtlefuse->eeprom_c9 & BIT(1)) |
3377 ((rtlefuse->eeprom_cc & BIT(1)) << 4));
3378 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,

--- 37 unchanged lines hidden (view full) ---

3416 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */
3417 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
3418 /* fc_area */
3419 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
3420 /* 5G LAN ON */
3421 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
3422 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */
3423 if (rtlefuse->internal_pa_5g[0])
3424 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3424 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3425 0x2d4000b5);
3426 else
3425 0x2d4000b5);
3426 else
3427 rtl_set_bbreg(hw, ROFDM0_XATxIQIMBALANCE, MASKDWORD,
3427 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
3428 0x20000080);
3429 if (rtlefuse->internal_pa_5g[1])
3428 0x20000080);
3429 if (rtlefuse->internal_pa_5g[1])
3430 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3430 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3431 0x2d4000b5);
3432 else
3431 0x2d4000b5);
3432 else
3433 rtl_set_bbreg(hw, ROFDM0_XBTxIQIMBALANCE, MASKDWORD,
3433 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
3434 0x20000080);
3435 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3436 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3437 BIT(10) | BIT(6) | BIT(5),
3438 (rtlefuse->eeprom_cc & BIT(5)));
3439 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3440 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3441 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15),

--- 12 unchanged lines hidden (view full) ---

3454 BIT(31) | BIT(15),
3455 ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
3456 ((rtlefuse->eeprom_cc & BIT(6)) << 10));
3457 }
3458 }
3459 /* update IQK related settings */
3460 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
3461 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
3434 0x20000080);
3435 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
3436 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
3437 BIT(10) | BIT(6) | BIT(5),
3438 (rtlefuse->eeprom_cc & BIT(5)));
3439 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10),
3440 ((rtlefuse->eeprom_cc & BIT(4)) >> 4));
3441 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15),

--- 12 unchanged lines hidden (view full) ---

3454 BIT(31) | BIT(15),
3455 ((rtlefuse->eeprom_cc & BIT(4)) >> 4) |
3456 ((rtlefuse->eeprom_cc & BIT(6)) << 10));
3457 }
3458 }
3459 /* update IQK related settings */
3460 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100);
3461 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100);
3462 rtl_set_bbreg(hw, ROFDM0_XCTxAFE, 0xF0000000, 0x00);
3462 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00);
3463 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3464 BIT(26) | BIT(24), 0x00);
3463 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(30) | BIT(28) |
3464 BIT(26) | BIT(24), 0x00);
3465 rtl_set_bbreg(hw, ROFDM0_XDTxAFE, 0xF0000000, 0x00);
3465 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00);
3466 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
3467 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
3468
3469 /* Update RF */
3470 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3471 rfpath++) {
3472 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3473 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */

--- 91 unchanged lines hidden --- 		3466 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00);
3467 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00);
3468
3469 /* Update RF */
3470 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
3471 rfpath++) {
3472 if (rtlhal->current_bandtype == BAND_ON_2_4G) {
3473 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */

--- 91 unchanged lines hidden ---