| phy.h (0770f718458ed93fe593b887fb7481c30999bea5) | phy.h (ff9704538e6dd8d652e98317ab3dc06c7a017e58) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4#ifndef __RTL92C_PHY_H__ 5#define __RTL92C_PHY_H__ 6 7#define MAX_PRECMD_CNT 16 8#define MAX_RFDEPENDCMD_CNT 16 --- 8 unchanged lines hidden (view full) --- 17 18#define APK_BB_REG_NUM 5 19#define APK_AFE_REG_NUM 16 20#define APK_CURVE_REG_NUM 4 21#define PATH_NUM 2 22 23#define LOOP_LIMIT 5 24#define MAX_STALL_TIME 50 | 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* Copyright(c) 2009-2012 Realtek Corporation.*/ 3 4#ifndef __RTL92C_PHY_H__ 5#define __RTL92C_PHY_H__ 6 7#define MAX_PRECMD_CNT 16 8#define MAX_RFDEPENDCMD_CNT 16 --- 8 unchanged lines hidden (view full) --- 17 18#define APK_BB_REG_NUM 5 19#define APK_AFE_REG_NUM 16 20#define APK_CURVE_REG_NUM 4 21#define PATH_NUM 2 22 23#define LOOP_LIMIT 5 24#define MAX_STALL_TIME 50 |
| 25#define AntennaDiversityValue 0x80 | 25#define ANTENNADIVERSITYVALUE 0x80 |
| 26#define MAX_TXPWR_IDX_NMODE_92S 63 | 26#define MAX_TXPWR_IDX_NMODE_92S 63 |
| 27#define Reset_Cnt_Limit 3 | 27#define RESET_CNT_LIMIT 3 |
| 28 29#define IQK_ADDA_REG_NUM 16 30#define IQK_MAC_REG_NUM 4 31 32#define IQK_DELAY_TIME 1 33 34#define RF90_PATH_MAX 2 35 --- 59 unchanged lines hidden (view full) --- 95u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw, 96 enum radio_path rfpath, u32 offset); 97u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask); 98void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw, 99 enum radio_path rfpath, u32 offset, u32 data); 100void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw, 101 enum radio_path rfpath, u32 offset, 102 u32 data); | 28 29#define IQK_ADDA_REG_NUM 16 30#define IQK_MAC_REG_NUM 4 31 32#define IQK_DELAY_TIME 1 33 34#define RF90_PATH_MAX 2 35 --- 59 unchanged lines hidden (view full) --- 95u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw, 96 enum radio_path rfpath, u32 offset); 97u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask); 98void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw, 99 enum radio_path rfpath, u32 offset, u32 data); 100void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw, 101 enum radio_path rfpath, u32 offset, 102 u32 data); |
| 103void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw, | 103void _rtl92c_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw, |
| 104 u32 regaddr, u32 bitmask, u32 data); 105bool _rtl92ce_phy_config_mac_with_headerfile(struct ieee80211_hw *hw); 106void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw); 107bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw); 108void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw); 109bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw, 110 enum rf_pwrstate rfpwr_state); 111bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 112 u8 configtype); 113bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, 114 u8 configtype); 115void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw); 116 117#endif | 104 u32 regaddr, u32 bitmask, u32 data); 105bool _rtl92ce_phy_config_mac_with_headerfile(struct ieee80211_hw *hw); 106void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw); 107bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw); 108void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw); 109bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw, 110 enum rf_pwrstate rfpwr_state); 111bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw, 112 u8 configtype); 113bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw, 114 u8 configtype); 115void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw); 116 117#endif |