regs.h (849ee6ac9dd3efd0a57cbc98b9a9d6ae87374aff) regs.h (0d2afe09fad5f8c59e21630f10b66b08cf5c529a)
1/* SPDX-License-Identifier: ISC */
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#ifndef __MT7921_REGS_H
5#define __MT7921_REGS_H
6
7/* MCU WFDMA1 */
8#define MT_MCU_WFDMA1_BASE 0x3000

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348 GENMASK(18, 4))
349
350#define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
351#define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
352#define MT_WFDMA0_GLO_CFG_TX_DMA_BUSY BIT(1)
353#define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
354#define MT_WFDMA0_GLO_CFG_RX_DMA_BUSY BIT(3)
355#define MT_WFDMA0_GLO_CFG_TX_WB_DDONE BIT(6)
1/* SPDX-License-Identifier: ISC */
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#ifndef __MT7921_REGS_H
5#define __MT7921_REGS_H
6
7/* MCU WFDMA1 */
8#define MT_MCU_WFDMA1_BASE 0x3000

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348 GENMASK(18, 4))
349
350#define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
351#define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
352#define MT_WFDMA0_GLO_CFG_TX_DMA_BUSY BIT(1)
353#define MT_WFDMA0_GLO_CFG_RX_DMA_EN BIT(2)
354#define MT_WFDMA0_GLO_CFG_RX_DMA_BUSY BIT(3)
355#define MT_WFDMA0_GLO_CFG_TX_WB_DDONE BIT(6)
356#define MT_WFDMA0_GLO_CFG_FW_DWLD_BYPASS_DMASHDL BIT(9)
356#define MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)
357#define MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN BIT(15)
358#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
359#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27)
360#define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28)
361#define MT_WFDMA0_GLO_CFG_CLK_GAT_DIS BIT(30)
362
363#define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)

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372#define MT_WFDMA0_TX_RING2_EXT_CTRL MT_WFDMA0(0x608)
373#define MT_WFDMA0_TX_RING3_EXT_CTRL MT_WFDMA0(0x60c)
374#define MT_WFDMA0_TX_RING4_EXT_CTRL MT_WFDMA0(0x610)
375#define MT_WFDMA0_TX_RING5_EXT_CTRL MT_WFDMA0(0x614)
376#define MT_WFDMA0_TX_RING6_EXT_CTRL MT_WFDMA0(0x618)
377#define MT_WFDMA0_TX_RING16_EXT_CTRL MT_WFDMA0(0x640)
378#define MT_WFDMA0_TX_RING17_EXT_CTRL MT_WFDMA0(0x644)
379
357#define MT_WFDMA0_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)
358#define MT_WFDMA0_GLO_CFG_CSR_DISP_BASE_PTR_CHAIN_EN BIT(15)
359#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21)
360#define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27)
361#define MT_WFDMA0_GLO_CFG_OMIT_TX_INFO BIT(28)
362#define MT_WFDMA0_GLO_CFG_CLK_GAT_DIS BIT(30)
363
364#define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)

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373#define MT_WFDMA0_TX_RING2_EXT_CTRL MT_WFDMA0(0x608)
374#define MT_WFDMA0_TX_RING3_EXT_CTRL MT_WFDMA0(0x60c)
375#define MT_WFDMA0_TX_RING4_EXT_CTRL MT_WFDMA0(0x610)
376#define MT_WFDMA0_TX_RING5_EXT_CTRL MT_WFDMA0(0x614)
377#define MT_WFDMA0_TX_RING6_EXT_CTRL MT_WFDMA0(0x618)
378#define MT_WFDMA0_TX_RING16_EXT_CTRL MT_WFDMA0(0x640)
379#define MT_WFDMA0_TX_RING17_EXT_CTRL MT_WFDMA0(0x644)
380
381#define MT_WPDMA0_MAX_CNT_MASK GENMASK(7, 0)
382#define MT_WPDMA0_BASE_PTR_MASK GENMASK(31, 16)
383
380#define MT_WFDMA0_RX_RING0_EXT_CTRL MT_WFDMA0(0x680)
381#define MT_WFDMA0_RX_RING1_EXT_CTRL MT_WFDMA0(0x684)
382#define MT_WFDMA0_RX_RING2_EXT_CTRL MT_WFDMA0(0x688)
383#define MT_WFDMA0_RX_RING3_EXT_CTRL MT_WFDMA0(0x68c)
384#define MT_WFDMA0_RX_RING4_EXT_CTRL MT_WFDMA0(0x690)
385#define MT_WFDMA0_RX_RING5_EXT_CTRL MT_WFDMA0(0x694)
386
387#define MT_TX_RING_BASE MT_WFDMA0(0x300)

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420#define MT_TOP_MISC_FW_STATE GENMASK(2, 0)
421
422#define MT_MCU_WPDMA0_BASE 0x54000000
423#define MT_MCU_WPDMA0(ofs) (MT_MCU_WPDMA0_BASE + (ofs))
424
425#define MT_WFDMA_DUMMY_CR MT_MCU_WPDMA0(0x120)
426#define MT_WFDMA_NEED_REINIT BIT(1)
427
384#define MT_WFDMA0_RX_RING0_EXT_CTRL MT_WFDMA0(0x680)
385#define MT_WFDMA0_RX_RING1_EXT_CTRL MT_WFDMA0(0x684)
386#define MT_WFDMA0_RX_RING2_EXT_CTRL MT_WFDMA0(0x688)
387#define MT_WFDMA0_RX_RING3_EXT_CTRL MT_WFDMA0(0x68c)
388#define MT_WFDMA0_RX_RING4_EXT_CTRL MT_WFDMA0(0x690)
389#define MT_WFDMA0_RX_RING5_EXT_CTRL MT_WFDMA0(0x694)
390
391#define MT_TX_RING_BASE MT_WFDMA0(0x300)

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424#define MT_TOP_MISC_FW_STATE GENMASK(2, 0)
425
426#define MT_MCU_WPDMA0_BASE 0x54000000
427#define MT_MCU_WPDMA0(ofs) (MT_MCU_WPDMA0_BASE + (ofs))
428
429#define MT_WFDMA_DUMMY_CR MT_MCU_WPDMA0(0x120)
430#define MT_WFDMA_NEED_REINIT BIT(1)
431
432#define MT_CBTOP_RGU(ofs) (0x70002000 + (ofs))
433#define MT_CBTOP_RGU_WF_SUBSYS_RST MT_CBTOP_RGU(0x600)
434#define MT_CBTOP_RGU_WF_SUBSYS_RST_WF_WHOLE_PATH BIT(0)
435
428#define MT_HW_BOUND 0x70010020
429#define MT_HW_CHIPID 0x70010200
430#define MT_HW_REV 0x70010204
431
432#define MT_PCIE_MAC_BASE 0x10000
433#define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs))
434#define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188)
435
436#define MT_HW_BOUND 0x70010020
437#define MT_HW_CHIPID 0x70010200
438#define MT_HW_REV 0x70010204
439
440#define MT_PCIE_MAC_BASE 0x10000
441#define MT_PCIE_MAC(ofs) (MT_PCIE_MAC_BASE + (ofs))
442#define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188)
443
436#define MT_DMA_SHDL(ofs) (0xd6000 + (ofs))
444#define MT_DMA_SHDL(ofs) (0x7c026000 + (ofs))
437#define MT_DMASHDL_SW_CONTROL MT_DMA_SHDL(0x004)
438#define MT_DMASHDL_DMASHDL_BYPASS BIT(28)
439#define MT_DMASHDL_OPTIONAL MT_DMA_SHDL(0x008)
440#define MT_DMASHDL_PAGE MT_DMA_SHDL(0x00c)
445#define MT_DMASHDL_SW_CONTROL MT_DMA_SHDL(0x004)
446#define MT_DMASHDL_DMASHDL_BYPASS BIT(28)
447#define MT_DMASHDL_OPTIONAL MT_DMA_SHDL(0x008)
448#define MT_DMASHDL_PAGE MT_DMA_SHDL(0x00c)
449#define MT_DMASHDL_GROUP_SEQ_ORDER BIT(16)
441#define MT_DMASHDL_REFILL MT_DMA_SHDL(0x010)
450#define MT_DMASHDL_REFILL MT_DMA_SHDL(0x010)
451#define MT_DMASHDL_REFILL_MASK GENMASK(31, 16)
442#define MT_DMASHDL_PKT_MAX_SIZE MT_DMA_SHDL(0x01c)
443#define MT_DMASHDL_PKT_MAX_SIZE_PLE GENMASK(11, 0)
444#define MT_DMASHDL_PKT_MAX_SIZE_PSE GENMASK(27, 16)
445
446#define MT_DMASHDL_GROUP_QUOTA(_n) MT_DMA_SHDL(0x020 + ((_n) << 2))
447#define MT_DMASHDL_GROUP_QUOTA_MIN GENMASK(11, 0)
448#define MT_DMASHDL_GROUP_QUOTA_MAX GENMASK(27, 16)
449
450#define MT_DMASHDL_Q_MAP(_n) MT_DMA_SHDL(0x060 + ((_n) << 2))
451#define MT_DMASHDL_Q_MAP_MASK GENMASK(3, 0)
452#define MT_DMASHDL_Q_MAP_SHIFT(_n) (4 * ((_n) % 8))
453
454#define MT_DMASHDL_SCHED_SET(_n) MT_DMA_SHDL(0x070 + ((_n) << 2))
455
452#define MT_DMASHDL_PKT_MAX_SIZE MT_DMA_SHDL(0x01c)
453#define MT_DMASHDL_PKT_MAX_SIZE_PLE GENMASK(11, 0)
454#define MT_DMASHDL_PKT_MAX_SIZE_PSE GENMASK(27, 16)
455
456#define MT_DMASHDL_GROUP_QUOTA(_n) MT_DMA_SHDL(0x020 + ((_n) << 2))
457#define MT_DMASHDL_GROUP_QUOTA_MIN GENMASK(11, 0)
458#define MT_DMASHDL_GROUP_QUOTA_MAX GENMASK(27, 16)
459
460#define MT_DMASHDL_Q_MAP(_n) MT_DMA_SHDL(0x060 + ((_n) << 2))
461#define MT_DMASHDL_Q_MAP_MASK GENMASK(3, 0)
462#define MT_DMASHDL_Q_MAP_SHIFT(_n) (4 * ((_n) % 8))
463
464#define MT_DMASHDL_SCHED_SET(_n) MT_DMA_SHDL(0x070 + ((_n) << 2))
465
466#define MT_WFDMA_HOST_CONFIG 0x7c027030
467#define MT_WFDMA_HOST_CONFIG_USB_RXEVT_EP4_EN BIT(6)
468
469#define MT_UMAC(ofs) (0x74000000 + (ofs))
470#define MT_UDMA_TX_QSEL MT_UMAC(0x008)
471#define MT_FW_DL_EN BIT(3)
472
473#define MT_UDMA_WLCFG_1 MT_UMAC(0x00c)
474#define MT_WL_RX_AGG_PKT_LMT GENMASK(7, 0)
475#define MT_WL_TX_TMOUT_LMT GENMASK(27, 8)
476
477#define MT_UDMA_WLCFG_0 MT_UMAC(0x18)
478#define MT_WL_RX_AGG_TO GENMASK(7, 0)
479#define MT_WL_RX_AGG_LMT GENMASK(15, 8)
480#define MT_WL_TX_TMOUT_FUNC_EN BIT(16)
481#define MT_WL_TX_DPH_CHK_EN BIT(17)
482#define MT_WL_RX_MPSZ_PAD0 BIT(18)
483#define MT_WL_RX_FLUSH BIT(19)
484#define MT_TICK_1US_EN BIT(20)
485#define MT_WL_RX_AGG_EN BIT(21)
486#define MT_WL_RX_EN BIT(22)
487#define MT_WL_TX_EN BIT(23)
488#define MT_WL_RX_BUSY BIT(30)
489#define MT_WL_TX_BUSY BIT(31)
490
491#define MT_UDMA_CONN_INFRA_STATUS MT_UMAC(0xa20)
492#define MT_UDMA_CONN_WFSYS_INIT_DONE BIT(22)
493#define MT_UDMA_CONN_INFRA_STATUS_SEL MT_UMAC(0xa24)
494
495#define MT_SSUSB_EPCTL_CSR(ofs) (0x74011800 + (ofs))
496#define MT_SSUSB_EPCTL_CSR_EP_RST_OPT MT_SSUSB_EPCTL_CSR(0x090)
497
498#define MT_UWFDMA0(ofs) (0x7c024000 + (ofs))
499#define MT_UWFDMA0_GLO_CFG MT_UWFDMA0(0x208)
500#define MT_UWFDMA0_GLO_CFG_EXT0 MT_UWFDMA0(0x2b0)
501#define MT_UWFDMA0_TX_RING_EXT_CTRL(_n) MT_UWFDMA0(0x600 + ((_n) << 2))
502
456#define MT_CONN_STATUS 0x7c053c10
457#define MT_WIFI_PATCH_DL_STATE BIT(0)
458
459#define MT_CONN_ON_LPCTL 0x7c060010
460#define PCIE_LPCR_HOST_OWN_SYNC BIT(2)
461#define PCIE_LPCR_HOST_CLR_OWN BIT(1)
462#define PCIE_LPCR_HOST_SET_OWN BIT(0)
463
464#define MT_WFSYS_SW_RST_B 0x18000140
465#define WFSYS_SW_RST_B BIT(0)
466#define WFSYS_SW_INIT_DONE BIT(4)
467
468#define MT_CONN_ON_MISC 0x7c0600f0
503#define MT_CONN_STATUS 0x7c053c10
504#define MT_WIFI_PATCH_DL_STATE BIT(0)
505
506#define MT_CONN_ON_LPCTL 0x7c060010
507#define PCIE_LPCR_HOST_OWN_SYNC BIT(2)
508#define PCIE_LPCR_HOST_CLR_OWN BIT(1)
509#define PCIE_LPCR_HOST_SET_OWN BIT(0)
510
511#define MT_WFSYS_SW_RST_B 0x18000140
512#define WFSYS_SW_RST_B BIT(0)
513#define WFSYS_SW_INIT_DONE BIT(4)
514
515#define MT_CONN_ON_MISC 0x7c0600f0
516#define MT_TOP_MISC2_FW_PWR_ON BIT(0)
469#define MT_TOP_MISC2_FW_N9_RDY GENMASK(1, 0)
470
471#endif
517#define MT_TOP_MISC2_FW_N9_RDY GENMASK(1, 0)
518
519#endif