mcu.h (ffa1bf97425bd511b105ce769976e20a845a71e9) | mcu.h (67aa27431c7f871962fccdb70ae1f3883691e958) |
---|---|
1/* SPDX-License-Identifier: ISC */ 2/* Copyright (C) 2020 MediaTek Inc. */ 3 4#ifndef __MT7921_MCU_H 5#define __MT7921_MCU_H 6 | 1/* SPDX-License-Identifier: ISC */ 2/* Copyright (C) 2020 MediaTek Inc. */ 3 4#ifndef __MT7921_MCU_H 5#define __MT7921_MCU_H 6 |
7#include "../mt76_connac_mcu.h" 8 |
|
7struct mt7921_mcu_txd { 8 __le32 txd[8]; 9 10 __le16 len; 11 __le16 pq_id; 12 13 u8 cid; 14 u8 pkt_type; --- 114 unchanged lines hidden (view full) --- 129 130enum { 131 MCU_S2D_H2N, 132 MCU_S2D_C2N, 133 MCU_S2D_H2C, 134 MCU_S2D_H2CN 135}; 136 | 9struct mt7921_mcu_txd { 10 __le32 txd[8]; 11 12 __le16 len; 13 __le16 pq_id; 14 15 u8 cid; 16 u8 pkt_type; --- 114 unchanged lines hidden (view full) --- 131 132enum { 133 MCU_S2D_H2N, 134 MCU_S2D_C2N, 135 MCU_S2D_H2C, 136 MCU_S2D_H2CN 137}; 138 |
137#define MCU_FW_PREFIX BIT(31) 138#define MCU_UNI_PREFIX BIT(30) 139#define MCU_CE_PREFIX BIT(29) 140#define MCU_QUERY_PREFIX BIT(28) 141#define MCU_CMD_MASK ~(MCU_FW_PREFIX | MCU_UNI_PREFIX | \ 142 MCU_CE_PREFIX | MCU_QUERY_PREFIX) 143 144#define MCU_QUERY_MASK BIT(16) 145 146enum { 147 MCU_CMD_TARGET_ADDRESS_LEN_REQ = MCU_FW_PREFIX | 0x01, 148 MCU_CMD_FW_START_REQ = MCU_FW_PREFIX | 0x02, 149 MCU_CMD_NIC_POWER_CTRL = MCU_FW_PREFIX | 0x4, 150 MCU_CMD_PATCH_START_REQ = MCU_FW_PREFIX | 0x05, 151 MCU_CMD_PATCH_FINISH_REQ = MCU_FW_PREFIX | 0x07, 152 MCU_CMD_PATCH_SEM_CONTROL = MCU_FW_PREFIX | 0x10, 153 MCU_CMD_EXT_CID = 0xED, 154 MCU_CMD_FW_SCATTER = MCU_FW_PREFIX | 0xEE, 155}; 156 157enum { 158 MCU_EXT_CMD_EFUSE_ACCESS = 0x01, 159 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 160 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 161 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 162 MCU_EXT_CMD_THERMAL_CTRL = 0x2c, 163 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 164 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 165 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 166 MCU_EXT_CMD_RX_HDR_TRANS = 0x47, 167 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 168}; 169 170enum { 171 MCU_UNI_CMD_DEV_INFO_UPDATE = MCU_UNI_PREFIX | 0x01, 172 MCU_UNI_CMD_BSS_INFO_UPDATE = MCU_UNI_PREFIX | 0x02, 173 MCU_UNI_CMD_STA_REC_UPDATE = MCU_UNI_PREFIX | 0x03, 174 MCU_UNI_CMD_SUSPEND = MCU_UNI_PREFIX | 0x05, 175 MCU_UNI_CMD_OFFLOAD = MCU_UNI_PREFIX | 0x06, 176 MCU_UNI_CMD_HIF_CTRL = MCU_UNI_PREFIX | 0x07, 177}; 178 | |
179struct mt7921_mcu_uni_event { 180 u8 cid; 181 u8 pad[3]; 182 __le32 status; /* 0: success, others: fail */ 183} __packed; 184 | 139struct mt7921_mcu_uni_event { 140 u8 cid; 141 u8 pad[3]; 142 __le32 status; /* 0: success, others: fail */ 143} __packed; 144 |
185enum { 186 WOW_USB = 1, 187 WOW_PCIE = 2, 188 WOW_GPIO = 3, 189}; 190 | |
191struct mt7921_wow_ctrl_tlv { 192 __le16 tag; 193 __le16 len; 194 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START 195 * 0x2: PM_WOWLAN_REQ_STOP 196 * 0x3: PM_WOWLAN_PARAM_CLEAR 197 */ 198 u8 trigger; /* 0: NONE --- 77 unchanged lines hidden (view full) --- 276 __le16 tag; 277 __le16 len; 278 u8 mode; 279 u8 ips_num; 280 u8 option; 281 u8 pad[1]; 282} __packed; 283 | 145struct mt7921_wow_ctrl_tlv { 146 __le16 tag; 147 __le16 len; 148 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START 149 * 0x2: PM_WOWLAN_REQ_STOP 150 * 0x3: PM_WOWLAN_PARAM_CLEAR 151 */ 152 u8 trigger; /* 0: NONE --- 77 unchanged lines hidden (view full) --- 230 __le16 tag; 231 __le16 len; 232 u8 mode; 233 u8 ips_num; 234 u8 option; 235 u8 pad[1]; 236} __packed; 237 |
284/* offload mcu commands */ | |
285enum { | 238enum { |
286 MCU_CMD_START_HW_SCAN = MCU_CE_PREFIX | 0x03, 287 MCU_CMD_SET_CHAN_DOMAIN = MCU_CE_PREFIX | 0x0f, 288 MCU_CMD_SET_BSS_CONNECTED = MCU_CE_PREFIX | 0x16, 289 MCU_CMD_SET_BSS_ABORT = MCU_CE_PREFIX | 0x17, 290 MCU_CMD_CANCEL_HW_SCAN = MCU_CE_PREFIX | 0x1b, 291 MCU_CMD_SCHED_SCAN_ENABLE = MCU_CE_PREFIX | 0x61, 292 MCU_CMD_SCHED_SCAN_REQ = MCU_CE_PREFIX | 0x62, 293 MCU_CMD_REG_WRITE = MCU_CE_PREFIX | 0xc0, 294 MCU_CMD_REG_READ = MCU_CE_PREFIX | MCU_QUERY_MASK | 0xc0, 295 MCU_CMD_FWLOG_2_HOST = MCU_CE_PREFIX | 0xc5, 296 MCU_CMD_GET_WTBL = MCU_CE_PREFIX | 0xcd, 297}; 298 299#define MCU_CMD_ACK BIT(0) 300#define MCU_CMD_UNI BIT(1) 301#define MCU_CMD_QUERY BIT(2) 302 303#define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | MCU_CMD_QUERY) 304 305enum { 306 UNI_BSS_INFO_BASIC = 0, 307 UNI_BSS_INFO_RLM = 2, 308 UNI_BSS_INFO_HE_BASIC = 5, 309 UNI_BSS_INFO_BCN_CONTENT = 7, 310 UNI_BSS_INFO_QBSS = 15, 311 UNI_BSS_INFO_UAPSD = 19, 312 UNI_BSS_INFO_PS = 21, 313 UNI_BSS_INFO_BCNFT = 22, 314}; 315 316enum { 317 UNI_SUSPEND_MODE_SETTING, 318 UNI_SUSPEND_WOW_CTRL, 319 UNI_SUSPEND_WOW_GPIO_PARAM, 320 UNI_SUSPEND_WOW_WAKEUP_PORT, 321 UNI_SUSPEND_WOW_PATTERN, 322}; 323 324enum { 325 UNI_OFFLOAD_OFFLOAD_ARP, 326 UNI_OFFLOAD_OFFLOAD_ND, 327 UNI_OFFLOAD_OFFLOAD_GTK_REKEY, 328 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT, 329}; 330 331enum { 332 PATCH_SEM_RELEASE, 333 PATCH_SEM_GET 334}; 335 336enum { | |
337 PATCH_NOT_DL_SEM_FAIL, 338 PATCH_IS_DL, 339 PATCH_NOT_DL_SEM_SUCCESS, 340 PATCH_REL_SEM_SUCCESS 341}; 342 343enum { 344 FW_STATE_INITIAL, --- 36 unchanged lines hidden (view full) --- 381#define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 382#define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 383#define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 384#define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 385#define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 386#define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 387#define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 388 | 239 PATCH_NOT_DL_SEM_FAIL, 240 PATCH_IS_DL, 241 PATCH_NOT_DL_SEM_SUCCESS, 242 PATCH_REL_SEM_SUCCESS 243}; 244 245enum { 246 FW_STATE_INITIAL, --- 36 unchanged lines hidden (view full) --- 283#define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 284#define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 285#define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 286#define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 287#define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 288#define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 289#define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 290 |
389#define CONN_STATE_DISCONNECT 0 390#define CONN_STATE_CONNECT 1 391#define CONN_STATE_PORT_SECURE 2 392 393enum { 394 DEV_INFO_ACTIVE, 395 DEV_INFO_MAX_NUM 396}; 397 398enum { 399 CMD_CBW_20MHZ = IEEE80211_STA_RX_BW_20, 400 CMD_CBW_40MHZ = IEEE80211_STA_RX_BW_40, 401 CMD_CBW_80MHZ = IEEE80211_STA_RX_BW_80, 402 CMD_CBW_160MHZ = IEEE80211_STA_RX_BW_160, 403 CMD_CBW_10MHZ, 404 CMD_CBW_5MHZ, 405 CMD_CBW_8080MHZ, 406 407 CMD_HE_MCS_BW80 = 0, 408 CMD_HE_MCS_BW160, 409 CMD_HE_MCS_BW8080, 410 CMD_HE_MCS_BW_NUM 411}; 412 413struct tlv { 414 __le16 tag; 415 __le16 len; 416} __packed; 417 418struct bss_info_uni_he { 419 __le16 tag; 420 __le16 len; 421 __le16 he_rts_thres; 422 u8 he_pe_duration; 423 u8 su_disable; 424 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 425 u8 rsv[2]; 426} __packed; 427 428enum { 429 WTBL_RESET_AND_SET = 1, 430 WTBL_SET, 431 WTBL_QUERY, 432 WTBL_RESET_ALL 433}; 434 435struct wtbl_req_hdr { 436 u8 wlan_idx_lo; 437 u8 operation; 438 __le16 tlv_num; 439 u8 wlan_idx_hi; 440 u8 rsv[3]; 441} __packed; 442 443struct wtbl_generic { 444 __le16 tag; 445 __le16 len; 446 u8 peer_addr[ETH_ALEN]; 447 u8 muar_idx; 448 u8 skip_tx; 449 u8 cf_ack; 450 u8 qos; 451 u8 mesh; 452 u8 adm; 453 __le16 partial_aid; 454 u8 baf_en; 455 u8 aad_om; 456} __packed; 457 458struct wtbl_rx { 459 __le16 tag; 460 __le16 len; 461 u8 rcid; 462 u8 rca1; 463 u8 rca2; 464 u8 rv; 465 u8 rsv[4]; 466} __packed; 467 468struct wtbl_ht { 469 __le16 tag; 470 __le16 len; 471 u8 ht; 472 u8 ldpc; 473 u8 af; 474 u8 mm; 475 u8 rsv[4]; 476} __packed; 477 478struct wtbl_vht { 479 __le16 tag; 480 __le16 len; 481 u8 ldpc; 482 u8 dyn_bw; 483 u8 vht; 484 u8 txop_ps; 485 u8 rsv[4]; 486} __packed; 487 488struct wtbl_hdr_trans { 489 __le16 tag; 490 __le16 len; 491 u8 to_ds; 492 u8 from_ds; 493 u8 no_rx_trans; 494 u8 _rsv; 495}; 496 497enum { 498 MT_BA_TYPE_INVALID, 499 MT_BA_TYPE_ORIGINATOR, 500 MT_BA_TYPE_RECIPIENT 501}; 502 503enum { 504 RST_BA_MAC_TID_MATCH, 505 RST_BA_MAC_MATCH, 506 RST_BA_NO_MATCH 507}; 508 509struct wtbl_ba { 510 __le16 tag; 511 __le16 len; 512 /* common */ 513 u8 tid; 514 u8 ba_type; 515 u8 rsv0[2]; 516 /* originator only */ 517 __le16 sn; 518 u8 ba_en; 519 u8 ba_winsize_idx; 520 __le16 ba_winsize; 521 /* recipient only */ 522 u8 peer_addr[ETH_ALEN]; 523 u8 rst_ba_tid; 524 u8 rst_ba_sel; 525 u8 rst_ba_sb; 526 u8 band_idx; 527 u8 rsv1[4]; 528} __packed; 529 530struct wtbl_smps { 531 __le16 tag; 532 __le16 len; 533 u8 smps; 534 u8 rsv[3]; 535} __packed; 536 537enum { 538 WTBL_GENERIC, 539 WTBL_RX, 540 WTBL_HT, 541 WTBL_VHT, 542 WTBL_PEER_PS, /* not used */ 543 WTBL_TX_PS, 544 WTBL_HDR_TRANS, 545 WTBL_SEC_KEY, 546 WTBL_BA, 547 WTBL_RDG, /* obsoleted */ 548 WTBL_PROTECT, /* not used */ 549 WTBL_CLEAR, /* not used */ 550 WTBL_BF, 551 WTBL_SMPS, 552 WTBL_RAW_DATA, /* debug only */ 553 WTBL_PN, 554 WTBL_SPE, 555 WTBL_MAX_NUM 556}; 557 558struct sta_ntlv_hdr { 559 u8 rsv[2]; 560 __le16 tlv_num; 561} __packed; 562 563struct sta_req_hdr { 564 u8 bss_idx; 565 u8 wlan_idx_lo; 566 __le16 tlv_num; 567 u8 is_tlv_append; 568 u8 muar_idx; 569 u8 wlan_idx_hi; 570 u8 rsv; 571} __packed; 572 573struct sta_rec_basic { 574 __le16 tag; 575 __le16 len; 576 __le32 conn_type; 577 u8 conn_state; 578 u8 qos; 579 __le16 aid; 580 u8 peer_addr[ETH_ALEN]; 581 __le16 extra_info; 582} __packed; 583 584struct sta_rec_ht { 585 __le16 tag; 586 __le16 len; 587 __le16 ht_cap; 588 u16 rsv; 589} __packed; 590 591struct sta_rec_vht { 592 __le16 tag; 593 __le16 len; 594 __le32 vht_cap; 595 __le16 vht_rx_mcs_map; 596 __le16 vht_tx_mcs_map; 597 u8 rts_bw_sig; 598 u8 rsv[3]; 599} __packed; 600 601struct sta_rec_uapsd { 602 __le16 tag; 603 __le16 len; 604 u8 dac_map; 605 u8 tac_map; 606 u8 max_sp; 607 u8 rsv0; 608 __le16 listen_interval; 609 u8 rsv1[2]; 610} __packed; 611 612struct sta_rec_he { 613 __le16 tag; 614 __le16 len; 615 616 __le32 he_cap; 617 618 u8 t_frame_dur; 619 u8 max_ampdu_exp; 620 u8 bw_set; 621 u8 device_class; 622 u8 dcm_tx_mode; 623 u8 dcm_tx_max_nss; 624 u8 dcm_rx_mode; 625 u8 dcm_rx_max_nss; 626 u8 dcm_max_ru; 627 u8 punc_pream_rx; 628 u8 pkt_ext; 629 u8 rsv1; 630 631 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM]; 632 633 u8 rsv2[2]; 634} __packed; 635 636struct sta_rec_ba { 637 __le16 tag; 638 __le16 len; 639 u8 tid; 640 u8 ba_type; 641 u8 amsdu; 642 u8 ba_en; 643 __le16 ssn; 644 __le16 winsize; 645} __packed; 646 647struct sta_rec_amsdu { 648 __le16 tag; 649 __le16 len; 650 u8 max_amsdu_num; 651 u8 max_mpdu_size; 652 u8 amsdu_en; 653 u8 rsv; 654} __packed; 655 | |
656struct sec_key { 657 u8 cipher_id; 658 u8 cipher_len; 659 u8 key_id; 660 u8 key_len; 661 u8 key[32]; 662} __packed; 663 664struct sta_rec_sec { 665 __le16 tag; 666 __le16 len; 667 u8 add; 668 u8 n_cipher; 669 u8 rsv[2]; 670 671 struct sec_key key[2]; 672} __packed; 673 | 291struct sec_key { 292 u8 cipher_id; 293 u8 cipher_len; 294 u8 key_id; 295 u8 key_len; 296 u8 key[32]; 297} __packed; 298 299struct sta_rec_sec { 300 __le16 tag; 301 __le16 len; 302 u8 add; 303 u8 n_cipher; 304 u8 rsv[2]; 305 306 struct sec_key key[2]; 307} __packed; 308 |
674struct sta_rec_state { 675 __le16 tag; 676 __le16 len; 677 __le32 flags; 678 u8 state; 679 u8 vht_opmode; 680 u8 action; 681 u8 rsv[1]; 682} __packed; 683 684#define HT_MCS_MASK_NUM 10 685 686struct sta_rec_ra_info { 687 __le16 tag; 688 __le16 len; 689 __le16 legacy; 690 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM]; 691} __packed; 692 693struct sta_rec_phy { 694 __le16 tag; 695 __le16 len; 696 __le16 basic_rate; 697 u8 phy_type; 698 u8 ampdu; 699 u8 rts_policy; 700 u8 rcpi; 701 u8 rsv[2]; 702} __packed; 703 704enum { 705 STA_REC_BASIC, 706 STA_REC_RA, 707 STA_REC_RA_CMM_INFO, 708 STA_REC_RA_UPDATE, 709 STA_REC_BF, 710 STA_REC_AMSDU, 711 STA_REC_BA, 712 STA_REC_STATE, 713 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 714 STA_REC_HT, 715 STA_REC_VHT, 716 STA_REC_APPS, 717 STA_REC_KEY, 718 STA_REC_WTBL, 719 STA_REC_HE, 720 STA_REC_HW_AMSDU, 721 STA_REC_WTBL_AADOM, 722 STA_REC_KEY_V2, 723 STA_REC_MURU, 724 STA_REC_MUEDCA, 725 STA_REC_BFEE, 726 STA_REC_PHY = 0x15, 727 STA_REC_MAX_NUM 728}; 729 | |
730enum mt7921_cipher_type { 731 MT_CIPHER_NONE, 732 MT_CIPHER_WEP40, 733 MT_CIPHER_WEP104, 734 MT_CIPHER_WEP128, 735 MT_CIPHER_TKIP, 736 MT_CIPHER_AES_CCMP, 737 MT_CIPHER_CCMP_256, --- 44 unchanged lines hidden (view full) --- 782 sizeof(struct sta_rec_uapsd) + \ 783 sizeof(struct sta_rec_amsdu) + \ 784 sizeof(struct tlv) + \ 785 MT7921_WTBL_UPDATE_MAX_SIZE) 786 787#define MT7921_WTBL_UPDATE_BA_SIZE (sizeof(struct wtbl_req_hdr) + \ 788 sizeof(struct wtbl_ba)) 789 | 309enum mt7921_cipher_type { 310 MT_CIPHER_NONE, 311 MT_CIPHER_WEP40, 312 MT_CIPHER_WEP104, 313 MT_CIPHER_WEP128, 314 MT_CIPHER_TKIP, 315 MT_CIPHER_AES_CCMP, 316 MT_CIPHER_CCMP_256, --- 44 unchanged lines hidden (view full) --- 361 sizeof(struct sta_rec_uapsd) + \ 362 sizeof(struct sta_rec_amsdu) + \ 363 sizeof(struct tlv) + \ 364 MT7921_WTBL_UPDATE_MAX_SIZE) 365 366#define MT7921_WTBL_UPDATE_BA_SIZE (sizeof(struct wtbl_req_hdr) + \ 367 sizeof(struct wtbl_ba)) 368 |
790#define PHY_MODE_A BIT(0) 791#define PHY_MODE_B BIT(1) 792#define PHY_MODE_G BIT(2) 793#define PHY_MODE_GN BIT(3) 794#define PHY_MODE_AN BIT(4) 795#define PHY_MODE_AC BIT(5) 796#define PHY_MODE_AX_24G BIT(6) 797#define PHY_MODE_AX_5G BIT(7) 798#define PHY_MODE_AX_6G BIT(8) 799 800#define MODE_CCK BIT(0) 801#define MODE_OFDM BIT(1) 802#define MODE_HT BIT(2) 803#define MODE_VHT BIT(3) 804#define MODE_HE BIT(4) 805 | |
806#define STA_CAP_WMM BIT(0) 807#define STA_CAP_SGI_20 BIT(4) 808#define STA_CAP_SGI_40 BIT(5) 809#define STA_CAP_TX_STBC BIT(6) 810#define STA_CAP_RX_STBC BIT(7) 811#define STA_CAP_VHT_SGI_80 BIT(16) 812#define STA_CAP_VHT_SGI_160 BIT(17) 813#define STA_CAP_VHT_TX_STBC BIT(18) 814#define STA_CAP_VHT_RX_STBC BIT(19) 815#define STA_CAP_VHT_LDPC BIT(23) 816#define STA_CAP_LDPC BIT(24) 817#define STA_CAP_HT BIT(26) 818#define STA_CAP_VHT BIT(27) 819#define STA_CAP_HE BIT(28) 820 | 369#define STA_CAP_WMM BIT(0) 370#define STA_CAP_SGI_20 BIT(4) 371#define STA_CAP_SGI_40 BIT(5) 372#define STA_CAP_TX_STBC BIT(6) 373#define STA_CAP_RX_STBC BIT(7) 374#define STA_CAP_VHT_SGI_80 BIT(16) 375#define STA_CAP_VHT_SGI_160 BIT(17) 376#define STA_CAP_VHT_TX_STBC BIT(18) 377#define STA_CAP_VHT_RX_STBC BIT(19) 378#define STA_CAP_VHT_LDPC BIT(23) 379#define STA_CAP_LDPC BIT(24) 380#define STA_CAP_HT BIT(26) 381#define STA_CAP_VHT BIT(27) 382#define STA_CAP_HE BIT(28) 383 |
821/* HE MAC */ 822#define STA_REC_HE_CAP_HTC BIT(0) 823#define STA_REC_HE_CAP_BQR BIT(1) 824#define STA_REC_HE_CAP_BSR BIT(2) 825#define STA_REC_HE_CAP_OM BIT(3) 826#define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4) 827/* HE PHY */ 828#define STA_REC_HE_CAP_DUAL_BAND BIT(5) 829#define STA_REC_HE_CAP_LDPC BIT(6) 830#define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7) 831#define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8) 832/* STBC */ 833#define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9) 834#define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10) 835#define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11) 836#define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12) 837/* GI */ 838#define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13) 839#define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14) 840#define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15) 841#define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16) 842#define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17) 843/* 242 TONE */ 844#define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18) 845#define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19) 846#define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20) 847 | |
848struct mt7921_mcu_reg_event { 849 __le32 reg; 850 __le32 val; 851} __packed; 852 | 384struct mt7921_mcu_reg_event { 385 __le32 reg; 386 __le32 val; 387} __packed; 388 |
853struct mt7921_bss_basic_tlv { 854 __le16 tag; 855 __le16 len; 856 u8 active; 857 u8 omac_idx; 858 u8 hw_bss_idx; 859 u8 band_idx; 860 __le32 conn_type; 861 u8 conn_state; 862 u8 wmm_idx; 863 u8 bssid[ETH_ALEN]; 864 __le16 bmc_tx_wlan_idx; 865 __le16 bcn_interval; 866 u8 dtim_period; 867 u8 phymode; /* bit(0): A 868 * bit(1): B 869 * bit(2): G 870 * bit(3): GN 871 * bit(4): AN 872 * bit(5): AC 873 */ 874 __le16 sta_idx; 875 u8 nonht_basic_phy; 876 u8 pad[3]; 877} __packed; 878 879struct mt7921_bss_qos_tlv { 880 __le16 tag; 881 __le16 len; 882 u8 qos; 883 u8 pad[3]; 884} __packed; 885 886struct mt7921_beacon_loss_event { 887 u8 bss_idx; 888 u8 reason; 889 u8 pad[2]; 890} __packed; 891 | |
892struct mt7921_mcu_scan_ssid { 893 __le32 ssid_len; 894 u8 ssid[IEEE80211_MAX_SSID_LEN]; 895} __packed; 896 897struct mt7921_mcu_scan_channel { 898 u8 band; /* 1: 2.4GHz 899 * 2: 5.0GHz --- 100 unchanged lines hidden (view full) --- 1000 u8 intervals_num; 1001 u8 scan_func; 1002 struct mt7921_mcu_scan_channel channels[64]; 1003 __le16 intervals[MT7921_MAX_SCHED_SCAN_INTERVAL]; 1004 u8 bss_idx; 1005 u8 pad2[64]; 1006} __packed; 1007 | 389struct mt7921_mcu_scan_ssid { 390 __le32 ssid_len; 391 u8 ssid[IEEE80211_MAX_SSID_LEN]; 392} __packed; 393 394struct mt7921_mcu_scan_channel { 395 u8 band; /* 1: 2.4GHz 396 * 2: 5.0GHz --- 100 unchanged lines hidden (view full) --- 497 u8 intervals_num; 498 u8 scan_func; 499 struct mt7921_mcu_scan_channel channels[64]; 500 __le16 intervals[MT7921_MAX_SCHED_SCAN_INTERVAL]; 501 u8 bss_idx; 502 u8 pad2[64]; 503} __packed; 504 |
1008struct mt7921_mcu_bss_event { 1009 u8 bss_idx; 1010 u8 is_absent; 1011 u8 free_quota; 1012 u8 pad; 1013} __packed; 1014 1015enum { 1016 PHY_TYPE_HR_DSSS_INDEX = 0, 1017 PHY_TYPE_ERP_INDEX, 1018 PHY_TYPE_ERP_P2P_INDEX, 1019 PHY_TYPE_OFDM_INDEX, 1020 PHY_TYPE_HT_INDEX, 1021 PHY_TYPE_VHT_INDEX, 1022 PHY_TYPE_HE_INDEX, 1023 PHY_TYPE_INDEX_NUM 1024}; 1025 1026#define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX) 1027#define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX) 1028#define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX) 1029#define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX) 1030#define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX) 1031#define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX) 1032 1033#define MT_WTBL_RATE_TX_MODE GENMASK(9, 6) 1034#define MT_WTBL_RATE_MCS GENMASK(5, 0) 1035#define MT_WTBL_RATE_NSS GENMASK(12, 10) 1036#define MT_WTBL_RATE_HE_GI GENMASK(7, 4) 1037#define MT_WTBL_RATE_GI GENMASK(3, 0) 1038 | |
1039struct mt7921_mcu_tx_config { 1040 u8 peer_addr[ETH_ALEN]; 1041 u8 sw; 1042 u8 dis_rx_hdr_tran; 1043 1044 u8 aad_om; 1045 u8 pfmu_idx; 1046 __le16 partial_aid; --- 130 unchanged lines hidden --- | 505struct mt7921_mcu_tx_config { 506 u8 peer_addr[ETH_ALEN]; 507 u8 sw; 508 u8 dis_rx_hdr_tran; 509 510 u8 aad_om; 511 u8 pfmu_idx; 512 __le16 partial_aid; --- 130 unchanged lines hidden --- |