mac.c (c605d0ce025358d50209468ede7b15a3d2656c1a) mac.c (c74df1c067f2af0a3758a5ab02806f501473797c)
1// SPDX-License-Identifier: ISC
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#include <linux/devcoredump.h>
5#include <linux/etherdevice.h>
6#include <linux/timekeeping.h>
7#include "mt7921.h"
8#include "../dma.h"
9#include "../mt76_connac2_mac.h"
10#include "mcu.h"
11
12#define MT_WTBL_TXRX_CAP_RATE_OFFSET 7
13#define MT_WTBL_TXRX_RATE_G2_HE 24
14#define MT_WTBL_TXRX_RATE_G2 12
15
16#define MT_WTBL_AC0_CTT_OFFSET 20
17
1// SPDX-License-Identifier: ISC
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#include <linux/devcoredump.h>
5#include <linux/etherdevice.h>
6#include <linux/timekeeping.h>
7#include "mt7921.h"
8#include "../dma.h"
9#include "../mt76_connac2_mac.h"
10#include "mcu.h"
11
12#define MT_WTBL_TXRX_CAP_RATE_OFFSET 7
13#define MT_WTBL_TXRX_RATE_G2_HE 24
14#define MT_WTBL_TXRX_RATE_G2 12
15
16#define MT_WTBL_AC0_CTT_OFFSET 20
17
18bool mt7921_mac_wtbl_update(struct mt792x_dev *dev, int idx, u32 mask)
19{
20 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
21 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
22
23 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
24 0, 5000);
25}
26
18static u32 mt7921_mac_wtbl_lmac_addr(int idx, u8 offset)
19{
20 return MT_WTBL_LMAC_OFFS(idx, 0) + offset * 4;
21}
22
23static struct mt76_wcid *mt7921_rx_get_wcid(struct mt792x_dev *dev,
24 u16 idx, bool unicast)
25{

--- 12 unchanged lines hidden (view full) ---

38
39 sta = container_of(wcid, struct mt792x_sta, wcid);
40 if (!sta->vif)
41 return NULL;
42
43 return &sta->vif->sta.wcid;
44}
45
27static u32 mt7921_mac_wtbl_lmac_addr(int idx, u8 offset)
28{
29 return MT_WTBL_LMAC_OFFS(idx, 0) + offset * 4;
30}
31
32static struct mt76_wcid *mt7921_rx_get_wcid(struct mt792x_dev *dev,
33 u16 idx, bool unicast)
34{

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47
48 sta = container_of(wcid, struct mt792x_sta, wcid);
49 if (!sta->vif)
50 return NULL;
51
52 return &sta->vif->sta.wcid;
53}
54
46bool mt7921_mac_wtbl_update(struct mt792x_dev *dev, int idx, u32 mask)
47{
48 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
49 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
50
51 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY,
52 0, 5000);
53}
54
55static void mt7921_mac_sta_poll(struct mt792x_dev *dev)
56{
57 static const u8 ac_to_tid[] = {
58 [IEEE80211_AC_BE] = 0,
59 [IEEE80211_AC_BK] = 1,
60 [IEEE80211_AC_VI] = 4,
61 [IEEE80211_AC_VO] = 6
62 };

--- 460 unchanged lines hidden (view full) ---

523 return;
524
525 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID);
526 pid = le32_get_bits(txs_data[3], MT_TXS3_PID);
527
528 if (pid < MT_PACKET_ID_FIRST)
529 return;
530
55static void mt7921_mac_sta_poll(struct mt792x_dev *dev)
56{
57 static const u8 ac_to_tid[] = {
58 [IEEE80211_AC_BE] = 0,
59 [IEEE80211_AC_BK] = 1,
60 [IEEE80211_AC_VI] = 4,
61 [IEEE80211_AC_VO] = 6
62 };

--- 460 unchanged lines hidden (view full) ---

523 return;
524
525 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID);
526 pid = le32_get_bits(txs_data[3], MT_TXS3_PID);
527
528 if (pid < MT_PACKET_ID_FIRST)
529 return;
530
531 if (wcidx >= MT7921_WTBL_SIZE)
531 if (wcidx >= MT792x_WTBL_SIZE)
532 return;
533
534 rcu_read_lock();
535
536 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
537 if (!wcid)
538 goto out;
539

--- 176 unchanged lines hidden (view full) ---

716 mt76_rr(dev, MT_MIB_SDR9(0));
717 mt76_rr(dev, MT_MIB_SDR36(0));
718 mt76_rr(dev, MT_MIB_SDR37(0));
719
720 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR);
721 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR);
722}
723
532 return;
533
534 rcu_read_lock();
535
536 wcid = rcu_dereference(dev->mt76.wcid[wcidx]);
537 if (!wcid)
538 goto out;
539

--- 176 unchanged lines hidden (view full) ---

716 mt76_rr(dev, MT_MIB_SDR9(0));
717 mt76_rr(dev, MT_MIB_SDR36(0));
718 mt76_rr(dev, MT_MIB_SDR37(0));
719
720 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR);
721 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR);
722}
723
724void mt7921_mac_set_timing(struct mt792x_phy *phy)
725{
726 s16 coverage_class = phy->coverage_class;
727 struct mt792x_dev *dev = phy->dev;
728 u32 val, reg_offset;
729 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
730 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
731 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
732 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);
733 bool is_2ghz = phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ;
734 int sifs = is_2ghz ? 10 : 16, offset;
735
736 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state))
737 return;
738
739 mt76_set(dev, MT_ARB_SCR(0),
740 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
741 udelay(1);
742
743 offset = 3 * coverage_class;
744 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
745 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
746
747 mt76_wr(dev, MT_TMAC_CDTR(0), cck + reg_offset);
748 mt76_wr(dev, MT_TMAC_ODTR(0), ofdm + reg_offset);
749 mt76_wr(dev, MT_TMAC_ICR0(0),
750 FIELD_PREP(MT_IFS_EIFS, 360) |
751 FIELD_PREP(MT_IFS_RIFS, 2) |
752 FIELD_PREP(MT_IFS_SIFS, sifs) |
753 FIELD_PREP(MT_IFS_SLOT, phy->slottime));
754
755 if (phy->slottime < 20 || !is_2ghz)
756 val = MT7921_CFEND_RATE_DEFAULT;
757 else
758 val = MT7921_CFEND_RATE_11B;
759
760 mt76_rmw_field(dev, MT_AGG_ACR0(0), MT_AGG_ACR_CFEND_RATE, val);
761 mt76_clear(dev, MT_ARB_SCR(0),
762 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
763}
764
765static u8
766mt7921_phy_get_nf(struct mt792x_phy *phy, int idx)
767{
768 return 0;
769}
770
771static void
772mt7921_phy_update_channel(struct mt76_phy *mphy, int idx)

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897
898 if (pm->suspended)
899 return;
900
901 queue_work(dev->mt76.wq, &dev->reset_work);
902}
903EXPORT_SYMBOL_GPL(mt7921_reset);
904
724static u8
725mt7921_phy_get_nf(struct mt792x_phy *phy, int idx)
726{
727 return 0;
728}
729
730static void
731mt7921_phy_update_channel(struct mt76_phy *mphy, int idx)

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856
857 if (pm->suspended)
858 return;
859
860 queue_work(dev->mt76.wq, &dev->reset_work);
861}
862EXPORT_SYMBOL_GPL(mt7921_reset);
863
905void mt7921_mac_update_mib_stats(struct mt792x_phy *phy)
906{
907 struct mt76_mib_stats *mib = &phy->mib;
908 struct mt792x_dev *dev = phy->dev;
909 int i, aggr0 = 0, aggr1;
910 u32 val;
911
912 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(0),
913 MT_MIB_SDR3_FCS_ERR_MASK);
914 mib->ack_fail_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR3(0),
915 MT_MIB_ACK_FAIL_COUNT_MASK);
916 mib->ba_miss_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR2(0),
917 MT_MIB_BA_FAIL_COUNT_MASK);
918 mib->rts_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR0(0),
919 MT_MIB_RTS_COUNT_MASK);
920 mib->rts_retries_cnt += mt76_get_field(dev, MT_MIB_MB_BSDR1(0),
921 MT_MIB_RTS_FAIL_COUNT_MASK);
922
923 mib->tx_ampdu_cnt += mt76_rr(dev, MT_MIB_SDR12(0));
924 mib->tx_mpdu_attempts_cnt += mt76_rr(dev, MT_MIB_SDR14(0));
925 mib->tx_mpdu_success_cnt += mt76_rr(dev, MT_MIB_SDR15(0));
926
927 val = mt76_rr(dev, MT_MIB_SDR32(0));
928 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR9_EBF_CNT_MASK, val);
929 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR9_IBF_CNT_MASK, val);
930
931 val = mt76_rr(dev, MT_ETBF_TX_APP_CNT(0));
932 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, val);
933 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, val);
934
935 val = mt76_rr(dev, MT_ETBF_RX_FB_CNT(0));
936 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, val);
937 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, val);
938 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, val);
939 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, val);
940
941 mib->rx_mpdu_cnt += mt76_rr(dev, MT_MIB_SDR5(0));
942 mib->rx_ampdu_cnt += mt76_rr(dev, MT_MIB_SDR22(0));
943 mib->rx_ampdu_bytes_cnt += mt76_rr(dev, MT_MIB_SDR23(0));
944 mib->rx_ba_cnt += mt76_rr(dev, MT_MIB_SDR31(0));
945
946 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) {
947 val = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i));
948 mib->tx_amsdu[i] += val;
949 mib->tx_amsdu_cnt += val;
950 }
951
952 for (i = 0, aggr1 = aggr0 + 8; i < 4; i++) {
953 u32 val2;
954
955 val = mt76_rr(dev, MT_TX_AGG_CNT(0, i));
956 val2 = mt76_rr(dev, MT_TX_AGG_CNT2(0, i));
957
958 phy->mt76->aggr_stats[aggr0++] += val & 0xffff;
959 phy->mt76->aggr_stats[aggr0++] += val >> 16;
960 phy->mt76->aggr_stats[aggr1++] += val2 & 0xffff;
961 phy->mt76->aggr_stats[aggr1++] += val2 >> 16;
962 }
963}
964
965void mt7921_mac_work(struct work_struct *work)
966{
967 struct mt792x_phy *phy;
968 struct mt76_phy *mphy;
969
970 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy,
971 mac_work.work);
972 phy = mphy->priv;
973
974 mt792x_mutex_acquire(phy->dev);
975
976 mt76_update_survey(mphy);
977 if (++mphy->mac_work_count == 2) {
978 mphy->mac_work_count = 0;
979
980 mt7921_mac_update_mib_stats(phy);
981 }
982
983 mt792x_mutex_release(phy->dev);
984
985 mt76_tx_status_check(mphy->dev, false);
986 ieee80211_queue_delayed_work(phy->mt76->hw, &mphy->mac_work,
987 MT7921_WATCHDOG_TIME);
988}
989
990void mt7921_pm_wake_work(struct work_struct *work)
991{
992 struct mt792x_dev *dev;
993 struct mt76_phy *mphy;
994
995 dev = (struct mt792x_dev *)container_of(work, struct mt792x_dev,
996 pm.wake_work);
997 mphy = dev->phy.mt76;

--- 10 unchanged lines hidden (view full) ---

1008 mt76_for_each_q_rx(mdev, i)
1009 napi_schedule(&mdev->napi[i]);
1010 local_bh_enable();
1011 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm);
1012 mt76_connac_tx_cleanup(mdev);
1013 }
1014 if (test_bit(MT76_STATE_RUNNING, &mphy->state))
1015 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work,
864void mt7921_pm_wake_work(struct work_struct *work)
865{
866 struct mt792x_dev *dev;
867 struct mt76_phy *mphy;
868
869 dev = (struct mt792x_dev *)container_of(work, struct mt792x_dev,
870 pm.wake_work);
871 mphy = dev->phy.mt76;

--- 10 unchanged lines hidden (view full) ---

882 mt76_for_each_q_rx(mdev, i)
883 napi_schedule(&mdev->napi[i]);
884 local_bh_enable();
885 mt76_connac_pm_dequeue_skbs(mphy, &dev->pm);
886 mt76_connac_tx_cleanup(mdev);
887 }
888 if (test_bit(MT76_STATE_RUNNING, &mphy->state))
889 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work,
1016 MT7921_WATCHDOG_TIME);
890 MT792x_WATCHDOG_TIME);
1017 }
1018
1019 ieee80211_wake_queues(mphy->hw);
1020 wake_up(&dev->pm.wait);
1021}
1022
1023void mt7921_pm_power_save_work(struct work_struct *work)
1024{

--- 202 unchanged lines hidden --- 		891 }
892
893 ieee80211_wake_queues(mphy->hw);
894 wake_up(&dev->pm.wait);
895}
896
897void mt7921_pm_power_save_work(struct work_struct *work)
898{

--- 202 unchanged lines hidden ---