mac.c (b7bfad2c83cdbbd7cd502bebdc75ef703c980634) mac.c (78562b2cafc61a0c08dc949eacb942ac756aae37)
1// SPDX-License-Identifier: ISC
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#include <linux/devcoredump.h>
5#include <linux/etherdevice.h>
6#include <linux/timekeeping.h>
7#include "mt7921.h"
8#include "../dma.h"

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235{
236 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM;
237 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
238 bool hdr_trans, unicast, insert_ccmp_hdr = false;
239 u8 chfreq, qos_ctl = 0, remove_pad, amsdu_info;
240 u16 hdr_gap;
241 __le32 *rxv = NULL, *rxd = (__le32 *)skb->data;
242 struct mt76_phy *mphy = &dev->mt76.phy;
1// SPDX-License-Identifier: ISC
2/* Copyright (C) 2020 MediaTek Inc. */
3
4#include <linux/devcoredump.h>
5#include <linux/etherdevice.h>
6#include <linux/timekeeping.h>
7#include "mt7921.h"
8#include "../dma.h"

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235{
236 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM;
237 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
238 bool hdr_trans, unicast, insert_ccmp_hdr = false;
239 u8 chfreq, qos_ctl = 0, remove_pad, amsdu_info;
240 u16 hdr_gap;
241 __le32 *rxv = NULL, *rxd = (__le32 *)skb->data;
242 struct mt76_phy *mphy = &dev->mt76.phy;
243 struct mt7921_phy *phy = &dev->phy;
243 struct mt792x_phy *phy = &dev->phy;
244 struct ieee80211_supported_band *sband;
245 u32 csum_status = *(u32 *)skb->cb;
246 u32 rxd0 = le32_to_cpu(rxd[0]);
247 u32 rxd1 = le32_to_cpu(rxd[1]);
248 u32 rxd2 = le32_to_cpu(rxd[2]);
249 u32 rxd3 = le32_to_cpu(rxd[3]);
250 u32 rxd4 = le32_to_cpu(rxd[4]);
251 struct mt792x_sta *msta = NULL;

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694 fallthrough;
695 default:
696 dev_kfree_skb(skb);
697 break;
698 }
699}
700EXPORT_SYMBOL_GPL(mt7921_queue_rx_skb);
701
244 struct ieee80211_supported_band *sband;
245 u32 csum_status = *(u32 *)skb->cb;
246 u32 rxd0 = le32_to_cpu(rxd[0]);
247 u32 rxd1 = le32_to_cpu(rxd[1]);
248 u32 rxd2 = le32_to_cpu(rxd[2]);
249 u32 rxd3 = le32_to_cpu(rxd[3]);
250 u32 rxd4 = le32_to_cpu(rxd[4]);
251 struct mt792x_sta *msta = NULL;

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694 fallthrough;
695 default:
696 dev_kfree_skb(skb);
697 break;
698 }
699}
700EXPORT_SYMBOL_GPL(mt7921_queue_rx_skb);
701
702void mt7921_mac_reset_counters(struct mt7921_phy *phy)
702void mt7921_mac_reset_counters(struct mt792x_phy *phy)
703{
704 struct mt7921_dev *dev = phy->dev;
705 int i;
706
707 for (i = 0; i < 4; i++) {
708 mt76_rr(dev, MT_TX_AGG_CNT(0, i));
709 mt76_rr(dev, MT_TX_AGG_CNT2(0, i));
710 }

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716 mt76_rr(dev, MT_MIB_SDR9(0));
717 mt76_rr(dev, MT_MIB_SDR36(0));
718 mt76_rr(dev, MT_MIB_SDR37(0));
719
720 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR);
721 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR);
722}
723
703{
704 struct mt7921_dev *dev = phy->dev;
705 int i;
706
707 for (i = 0; i < 4; i++) {
708 mt76_rr(dev, MT_TX_AGG_CNT(0, i));
709 mt76_rr(dev, MT_TX_AGG_CNT2(0, i));
710 }

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716 mt76_rr(dev, MT_MIB_SDR9(0));
717 mt76_rr(dev, MT_MIB_SDR36(0));
718 mt76_rr(dev, MT_MIB_SDR37(0));
719
720 mt76_set(dev, MT_WF_RMAC_MIB_TIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR);
721 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(0), MT_WF_RMAC_MIB_RXTIME_CLR);
722}
723
724void mt7921_mac_set_timing(struct mt7921_phy *phy)
724void mt7921_mac_set_timing(struct mt792x_phy *phy)
725{
726 s16 coverage_class = phy->coverage_class;
727 struct mt7921_dev *dev = phy->dev;
728 u32 val, reg_offset;
729 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
730 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
731 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
732 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);

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758 val = MT7921_CFEND_RATE_11B;
759
760 mt76_rmw_field(dev, MT_AGG_ACR0(0), MT_AGG_ACR_CFEND_RATE, val);
761 mt76_clear(dev, MT_ARB_SCR(0),
762 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
763}
764
765static u8
725{
726 s16 coverage_class = phy->coverage_class;
727 struct mt7921_dev *dev = phy->dev;
728 u32 val, reg_offset;
729 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
730 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
731 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
732 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28);

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758 val = MT7921_CFEND_RATE_11B;
759
760 mt76_rmw_field(dev, MT_AGG_ACR0(0), MT_AGG_ACR_CFEND_RATE, val);
761 mt76_clear(dev, MT_ARB_SCR(0),
762 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
763}
764
765static u8
766mt7921_phy_get_nf(struct mt7921_phy *phy, int idx)
766mt7921_phy_get_nf(struct mt792x_phy *phy, int idx)
767{
768 return 0;
769}
770
771static void
772mt7921_phy_update_channel(struct mt76_phy *mphy, int idx)
773{
774 struct mt7921_dev *dev = container_of(mphy->dev, struct mt7921_dev, mt76);
767{
768 return 0;
769}
770
771static void
772mt7921_phy_update_channel(struct mt76_phy *mphy, int idx)
773{
774 struct mt7921_dev *dev = container_of(mphy->dev, struct mt7921_dev, mt76);
775 struct mt7921_phy *phy = (struct mt7921_phy *)mphy->priv;
775 struct mt792x_phy *phy = (struct mt792x_phy *)mphy->priv;
776 struct mt76_channel_state *state;
777 u64 busy_time, tx_time, rx_time, obss_time;
778 int nf;
779
780 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
781 MT_MIB_SDR9_BUSY_MASK);
782 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx),
783 MT_MIB_SDR36_TXTIME_MASK);

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897
898 if (pm->suspended)
899 return;
900
901 queue_work(dev->mt76.wq, &dev->reset_work);
902}
903EXPORT_SYMBOL_GPL(mt7921_reset);
904
776 struct mt76_channel_state *state;
777 u64 busy_time, tx_time, rx_time, obss_time;
778 int nf;
779
780 busy_time = mt76_get_field(dev, MT_MIB_SDR9(idx),
781 MT_MIB_SDR9_BUSY_MASK);
782 tx_time = mt76_get_field(dev, MT_MIB_SDR36(idx),
783 MT_MIB_SDR36_TXTIME_MASK);

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897
898 if (pm->suspended)
899 return;
900
901 queue_work(dev->mt76.wq, &dev->reset_work);
902}
903EXPORT_SYMBOL_GPL(mt7921_reset);
904
905void mt7921_mac_update_mib_stats(struct mt7921_phy *phy)
905void mt7921_mac_update_mib_stats(struct mt792x_phy *phy)
906{
907 struct mt76_mib_stats *mib = &phy->mib;
908 struct mt7921_dev *dev = phy->dev;
909 int i, aggr0 = 0, aggr1;
910 u32 val;
911
912 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(0),
913 MT_MIB_SDR3_FCS_ERR_MASK);

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959 phy->mt76->aggr_stats[aggr0++] += val >> 16;
960 phy->mt76->aggr_stats[aggr1++] += val2 & 0xffff;
961 phy->mt76->aggr_stats[aggr1++] += val2 >> 16;
962 }
963}
964
965void mt7921_mac_work(struct work_struct *work)
966{
906{
907 struct mt76_mib_stats *mib = &phy->mib;
908 struct mt7921_dev *dev = phy->dev;
909 int i, aggr0 = 0, aggr1;
910 u32 val;
911
912 mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(0),
913 MT_MIB_SDR3_FCS_ERR_MASK);

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959 phy->mt76->aggr_stats[aggr0++] += val >> 16;
960 phy->mt76->aggr_stats[aggr1++] += val2 & 0xffff;
961 phy->mt76->aggr_stats[aggr1++] += val2 >> 16;
962 }
963}
964
965void mt7921_mac_work(struct work_struct *work)
966{
967 struct mt7921_phy *phy;
967 struct mt792x_phy *phy;
968 struct mt76_phy *mphy;
969
970 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy,
971 mac_work.work);
972 phy = mphy->priv;
973
974 mt7921_mutex_acquire(phy->dev);
975

--- 251 unchanged lines hidden --- 		968 struct mt76_phy *mphy;
969
970 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy,
971 mac_work.work);
972 phy = mphy->priv;
973
974 mt7921_mutex_acquire(phy->dev);
975

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