trans.c (1b6598c3dc35c631aa16279bb17f293c1b5c4ce8) trans.c (425d66d8ddfc4aaf692030aea67932dc59f69abf)
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Copyright (C) 2007-2015, 2018-2020 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7#include <linux/pci.h>
8#include <linux/interrupt.h>

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306 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
307
308 iwl_pcie_apm_config(trans);
309
310 /* Configure analog phase-lock-loop before activating to D0A */
311 if (trans->trans_cfg->base_params->pll_cfg)
312 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
313
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Copyright (C) 2007-2015, 2018-2020 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7#include <linux/pci.h>
8#include <linux/interrupt.h>

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306 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
307
308 iwl_pcie_apm_config(trans);
309
310 /* Configure analog phase-lock-loop before activating to D0A */
311 if (trans->trans_cfg->base_params->pll_cfg)
312 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
313
314 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
314 ret = iwl_finish_nic_init(trans);
315 if (ret)
316 return ret;
317
318 if (trans->cfg->host_interrupt_operation_mode) {
319 /*
320 * This is a bit of an abuse - This is needed for 7260 / 3160
321 * only check host_interrupt_operation_mode even if this is
322 * not related to host_interrupt_operation_mode.

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378 u32 dl_cfg_reg;
379
380 /* Force XTAL ON */
381 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
382 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
383
384 iwl_trans_pcie_sw_reset(trans);
385
315 if (ret)
316 return ret;
317
318 if (trans->cfg->host_interrupt_operation_mode) {
319 /*
320 * This is a bit of an abuse - This is needed for 7260 / 3160
321 * only check host_interrupt_operation_mode even if this is
322 * not related to host_interrupt_operation_mode.

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378 u32 dl_cfg_reg;
379
380 /* Force XTAL ON */
381 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
382 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
383
384 iwl_trans_pcie_sw_reset(trans);
385
386 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
386 ret = iwl_finish_nic_init(trans);
387 if (WARN_ON(ret)) {
388 /* Release XTAL ON request */
389 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
390 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
391 return;
392 }
393
394 /*

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1506 iwl_enable_interrupts(trans);
1507 *status = IWL_D3_STATUS_ALIVE;
1508 goto out;
1509 }
1510
1511 iwl_set_bit(trans, CSR_GP_CNTRL,
1512 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1513
387 if (WARN_ON(ret)) {
388 /* Release XTAL ON request */
389 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
390 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
391 return;
392 }
393
394 /*

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1506 iwl_enable_interrupts(trans);
1507 *status = IWL_D3_STATUS_ALIVE;
1508 goto out;
1509 }
1510
1511 iwl_set_bit(trans, CSR_GP_CNTRL,
1512 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1513
1514 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
1514 ret = iwl_finish_nic_init(trans);
1515 if (ret)
1516 return ret;
1517
1518 /*
1519 * Reconfigure IVAR table in case of MSIX or reset ict table in
1520 * MSI mode since HW reset erased it.
1521 * Also enables interrupts - none will happen as
1522 * the device doesn't know we're waking it up, only when

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1739
1740 return 0;
1741}
1742
1743static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1744{
1745 int ret;
1746
1515 if (ret)
1516 return ret;
1517
1518 /*
1519 * Reconfigure IVAR table in case of MSIX or reset ict table in
1520 * MSI mode since HW reset erased it.
1521 * Also enables interrupts - none will happen as
1522 * the device doesn't know we're waking it up, only when

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1739
1740 return 0;
1741}
1742
1743static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans)
1744{
1745 int ret;
1746
1747 ret = iwl_finish_nic_init(trans, trans->trans_cfg);
1747 ret = iwl_finish_nic_init(trans);
1748 if (ret < 0)
1749 return ret;
1750
1751 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1752 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1753 udelay(20);
1754 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1755 HPM_HIPM_GEN_CFG_CR_PG_EN |

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1748 if (ret < 0)
1749 return ret;
1750
1751 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1752 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE);
1753 udelay(20);
1754 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG,
1755 HPM_HIPM_GEN_CFG_CR_PG_EN |

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