trans.c (03c601927b673a243c9595e1ecc9e8adfdd02438) trans.c (d4f1a50ca998420e27f904128a8dac5f69c291ed)
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Copyright (C) 2007-2015, 2018-2022 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7#include <linux/pci.h>
8#include <linux/interrupt.h>

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126 trans_pcie->pcie_dbg_dumped_once = 1;
127 kfree(buf);
128}
129
130static int iwl_trans_pcie_sw_reset(struct iwl_trans *trans,
131 bool retake_ownership)
132{
133 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/*
3 * Copyright (C) 2007-2015, 2018-2022 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7#include <linux/pci.h>
8#include <linux/interrupt.h>

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126 trans_pcie->pcie_dbg_dumped_once = 1;
127 kfree(buf);
128}
129
130static int iwl_trans_pcie_sw_reset(struct iwl_trans *trans,
131 bool retake_ownership)
132{
133 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
134 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ)
134 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
135 iwl_set_bit(trans, CSR_GP_CNTRL,
136 CSR_GP_CNTRL_REG_FLAG_SW_RESET);
135 iwl_set_bit(trans, CSR_GP_CNTRL,
136 CSR_GP_CNTRL_REG_FLAG_SW_RESET);
137 else
137 usleep_range(10000, 20000);
138 } else {
138 iwl_set_bit(trans, CSR_RESET,
139 CSR_RESET_REG_FLAG_SW_RESET);
139 iwl_set_bit(trans, CSR_RESET,
140 CSR_RESET_REG_FLAG_SW_RESET);
140 usleep_range(5000, 6000);
141 usleep_range(5000, 6000);
142 }
141
142 if (retake_ownership)
143 return iwl_pcie_prepare_card_hw(trans);
144
145 return 0;
146}
147
148static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)

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470 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
471 iwl_set_bit(trans, CSR_GP_CNTRL,
472 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);
473
474 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
475 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
476 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
477 100);
143
144 if (retake_ownership)
145 return iwl_pcie_prepare_card_hw(trans);
146
147 return 0;
148}
149
150static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)

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472 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) {
473 iwl_set_bit(trans, CSR_GP_CNTRL,
474 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ);
475
476 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
477 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
478 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS,
479 100);
478 msleep(100);
480 usleep_range(10000, 20000);
479 } else {
480 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
481
482 ret = iwl_poll_bit(trans, CSR_RESET,
483 CSR_RESET_REG_FLAG_MASTER_DISABLED,
484 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
485 }
486

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1781 case IWL_DEVICE_FAMILY_22000:
1782 wprot = PREG_PRPH_WPROT_22000;
1783 break;
1784 default:
1785 return 0;
1786 }
1787
1788 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
481 } else {
482 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
483
484 ret = iwl_poll_bit(trans, CSR_RESET,
485 CSR_RESET_REG_FLAG_MASTER_DISABLED,
486 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
487 }
488

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1783 case IWL_DEVICE_FAMILY_22000:
1784 wprot = PREG_PRPH_WPROT_22000;
1785 break;
1786 default:
1787 return 0;
1788 }
1789
1790 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG);
1789 if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
1791 if (!iwl_trans_is_hw_error_value(hpm) && (hpm & PERSISTENCE_BIT)) {
1790 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
1791
1792 if (wprot_val & PREG_WFPM_ACCESS) {
1793 IWL_ERR(trans,
1794 "Error, can not clear persistence bit\n");
1795 return -EPERM;
1796 }
1797 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,

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1988 * do anything if NAPI was already initialized.
1989 */
1990 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1991 init_dummy_netdev(&trans_pcie->napi_dev);
1992
1993 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake;
1994}
1995
1792 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot);
1793
1794 if (wprot_val & PREG_WFPM_ACCESS) {
1795 IWL_ERR(trans,
1796 "Error, can not clear persistence bit\n");
1797 return -EPERM;
1798 }
1799 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG,

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1990 * do anything if NAPI was already initialized.
1991 */
1992 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1993 init_dummy_netdev(&trans_pcie->napi_dev);
1994
1995 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake;
1996}
1997
1998void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions,
1999 struct device *dev)
2000{
2001 u8 i;
2002 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc;
2003
2004 /* free DRAM payloads */
2005 for (i = 0; i < dram_regions->n_regions; i++) {
2006 dma_free_coherent(dev, dram_regions->drams[i].size,
2007 dram_regions->drams[i].block,
2008 dram_regions->drams[i].physical);
2009 }
2010 dram_regions->n_regions = 0;
2011
2012 /* free DRAM addresses array */
2013 if (desc_dram->block) {
2014 dma_free_coherent(dev, desc_dram->size,
2015 desc_dram->block,
2016 desc_dram->physical);
2017 }
2018 memset(desc_dram, 0, sizeof(*desc_dram));
2019}
2020
1996void iwl_trans_pcie_free(struct iwl_trans *trans)
1997{
1998 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1999 int i;
2000
2001 iwl_pcie_synchronize_irqs(trans);
2002
2003 if (trans->trans_cfg->gen2)

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2020
2021 trans_pcie->msix_enabled = false;
2022 } else {
2023 iwl_pcie_free_ict(trans);
2024 }
2025
2026 iwl_pcie_free_fw_monitor(trans);
2027
2021void iwl_trans_pcie_free(struct iwl_trans *trans)
2022{
2023 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2024 int i;
2025
2026 iwl_pcie_synchronize_irqs(trans);
2027
2028 if (trans->trans_cfg->gen2)

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2045
2046 trans_pcie->msix_enabled = false;
2047 } else {
2048 iwl_pcie_free_ict(trans);
2049 }
2050
2051 iwl_pcie_free_fw_monitor(trans);
2052
2028 if (trans_pcie->pnvm_dram.size)
2029 dma_free_coherent(trans->dev, trans_pcie->pnvm_dram.size,
2030 trans_pcie->pnvm_dram.block,
2031 trans_pcie->pnvm_dram.physical);
2053 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data,
2054 trans->dev);
2055 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->reduced_tables_data,
2056 trans->dev);
2032
2057
2033 if (trans_pcie->reduce_power_dram.size)
2034 dma_free_coherent(trans->dev,
2035 trans_pcie->reduce_power_dram.size,
2036 trans_pcie->reduce_power_dram.block,
2037 trans_pcie->reduce_power_dram.physical);
2038
2039 mutex_destroy(&trans_pcie->mutex);
2040 iwl_trans_free(trans);
2041}
2042
2043static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
2044{
2045 if (state)
2046 set_bit(STATUS_TPOWER_PMI, &trans->status);

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3529 .reclaim = iwl_txq_reclaim,
3530
3531 .set_q_ptrs = iwl_txq_set_q_ptrs,
3532
3533 .txq_alloc = iwl_txq_dyn_alloc,
3534 .txq_free = iwl_txq_dyn_free,
3535 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3536 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
2058 mutex_destroy(&trans_pcie->mutex);
2059 iwl_trans_free(trans);
2060}
2061
2062static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
2063{
2064 if (state)
2065 set_bit(STATUS_TPOWER_PMI, &trans->status);

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3548 .reclaim = iwl_txq_reclaim,
3549
3550 .set_q_ptrs = iwl_txq_set_q_ptrs,
3551
3552 .txq_alloc = iwl_txq_dyn_alloc,
3553 .txq_free = iwl_txq_dyn_free,
3554 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3555 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
3556 .load_pnvm = iwl_trans_pcie_ctx_info_gen3_load_pnvm,
3537 .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm,
3557 .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm,
3558 .load_reduce_power = iwl_trans_pcie_ctx_info_gen3_load_reduce_power,
3538 .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power,
3539#ifdef CONFIG_IWLWIFI_DEBUGFS
3540 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3541#endif
3542};
3543
3544struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3545 const struct pci_device_id *ent,

--- 197 unchanged lines hidden --- 		3559 .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power,
3560#ifdef CONFIG_IWLWIFI_DEBUGFS
3561 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup,
3562#endif
3563};
3564
3565struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3566 const struct pci_device_id *ent,

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