internal.h (de74c455fd991024be76a535df4d66e96af3896e) internal.h (eda50cde58de7368f982e3906090fc033ecb9360)
1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2015 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
5 * Copyright(c) 2016 Intel Deutschland GmbH
5 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
6 *
7 * Portions of this file are derived from the ipw3945 project, as well
8 * as portions of the ieee80211 subsystem header files.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *

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308 * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue.
309 */
310enum iwl_shared_irq_flags {
311 IWL_SHARED_IRQ_NON_RX = BIT(0),
312 IWL_SHARED_IRQ_FIRST_RSS = BIT(1),
313};
314
315/**
6 *
7 * Portions of this file are derived from the ipw3945 project, as well
8 * as portions of the ieee80211 subsystem header files.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *

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308 * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue.
309 */
310enum iwl_shared_irq_flags {
311 IWL_SHARED_IRQ_NON_RX = BIT(0),
312 IWL_SHARED_IRQ_FIRST_RSS = BIT(1),
313};
314
315/**
316 * struct iwl_dram_data
317 * @physical: page phy pointer
318 * @block: pointer to the allocated block/page
319 * @size: size of the block/page
320 */
321struct iwl_dram_data {
322 dma_addr_t physical;
323 void *block;
324 int size;
325};
326
327/**
328 * struct iwl_self_init_dram - dram data used by self init process
329 * @fw: lmac and umac dram data
330 * @fw_cnt: total number of items in array
331 * @paging: paging dram data
332 * @paging_cnt: total number of items in array
333 */
334struct iwl_self_init_dram {
335 struct iwl_dram_data *fw;
336 int fw_cnt;
337 struct iwl_dram_data *paging;
338 int paging_cnt;
339};
340
341/**
316 * struct iwl_trans_pcie - PCIe transport specific data
317 * @rxq: all the RX queue data
318 * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues
319 * @global_table: table mapping received VID from hw to rxb
320 * @rba: allocator for RX replenishing
342 * struct iwl_trans_pcie - PCIe transport specific data
343 * @rxq: all the RX queue data
344 * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues
345 * @global_table: table mapping received VID from hw to rxb
346 * @rba: allocator for RX replenishing
347 * @ctxt_info: context information for FW self init
348 * @ctxt_info_dma_addr: dma addr of context information
349 * @init_dram: DRAM data of firmware image (including paging).
350 * Context information addresses will be taken from here.
351 * This is driver's local copy for keeping track of size and
352 * count for allocating and freeing the memory.
321 * @trans: pointer to the generic transport area
322 * @scd_base_addr: scheduler sram base address in SRAM
323 * @scd_bc_tbls: pointer to the byte count table of the scheduler
324 * @kw: keep warm address
325 * @pci_dev: basic pci-network driver stuff
326 * @hw_base: pci hardware address support
327 * @ucode_write_complete: indicates that the ucode has been copied.
328 * @ucode_write_waitq: wait queue for uCode load

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350 * @fh_mask: current unmasked fh causes
351 * @hw_mask: current unmasked hw causes
352 */
353struct iwl_trans_pcie {
354 struct iwl_rxq *rxq;
355 struct iwl_rx_mem_buffer rx_pool[RX_POOL_SIZE];
356 struct iwl_rx_mem_buffer *global_table[RX_POOL_SIZE];
357 struct iwl_rb_allocator rba;
353 * @trans: pointer to the generic transport area
354 * @scd_base_addr: scheduler sram base address in SRAM
355 * @scd_bc_tbls: pointer to the byte count table of the scheduler
356 * @kw: keep warm address
357 * @pci_dev: basic pci-network driver stuff
358 * @hw_base: pci hardware address support
359 * @ucode_write_complete: indicates that the ucode has been copied.
360 * @ucode_write_waitq: wait queue for uCode load

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382 * @fh_mask: current unmasked fh causes
383 * @hw_mask: current unmasked hw causes
384 */
385struct iwl_trans_pcie {
386 struct iwl_rxq *rxq;
387 struct iwl_rx_mem_buffer rx_pool[RX_POOL_SIZE];
388 struct iwl_rx_mem_buffer *global_table[RX_POOL_SIZE];
389 struct iwl_rb_allocator rba;
390 struct iwl_context_info *ctxt_info;
391 dma_addr_t ctxt_info_dma_addr;
392 struct iwl_self_init_dram init_dram;
358 struct iwl_trans *trans;
359
360 struct net_device napi_dev;
361
362 struct __percpu iwl_tso_hdr_page *tso_hdr_page;
363
364 /* INT ICT Table */
365 __le32 *ict_tbl;

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447 const struct pci_device_id *ent,
448 const struct iwl_cfg *cfg);
449void iwl_trans_pcie_free(struct iwl_trans *trans);
450
451/*****************************************************
452* RX
453******************************************************/
454int iwl_pcie_rx_init(struct iwl_trans *trans);
393 struct iwl_trans *trans;
394
395 struct net_device napi_dev;
396
397 struct __percpu iwl_tso_hdr_page *tso_hdr_page;
398
399 /* INT ICT Table */
400 __le32 *ict_tbl;

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482 const struct pci_device_id *ent,
483 const struct iwl_cfg *cfg);
484void iwl_trans_pcie_free(struct iwl_trans *trans);
485
486/*****************************************************
487* RX
488******************************************************/
489int iwl_pcie_rx_init(struct iwl_trans *trans);
490int iwl_pcie_gen2_rx_init(struct iwl_trans *trans);
455irqreturn_t iwl_pcie_msix_isr(int irq, void *data);
456irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
457irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id);
458irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id);
459int iwl_pcie_rx_stop(struct iwl_trans *trans);
460void iwl_pcie_rx_free(struct iwl_trans *trans);
461
462/*****************************************************

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467void iwl_pcie_free_ict(struct iwl_trans *trans);
468void iwl_pcie_reset_ict(struct iwl_trans *trans);
469void iwl_pcie_disable_ict(struct iwl_trans *trans);
470
471/*****************************************************
472* TX / HCMD
473******************************************************/
474int iwl_pcie_tx_init(struct iwl_trans *trans);
491irqreturn_t iwl_pcie_msix_isr(int irq, void *data);
492irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
493irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id);
494irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id);
495int iwl_pcie_rx_stop(struct iwl_trans *trans);
496void iwl_pcie_rx_free(struct iwl_trans *trans);
497
498/*****************************************************

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503void iwl_pcie_free_ict(struct iwl_trans *trans);
504void iwl_pcie_reset_ict(struct iwl_trans *trans);
505void iwl_pcie_disable_ict(struct iwl_trans *trans);
506
507/*****************************************************
508* TX / HCMD
509******************************************************/
510int iwl_pcie_tx_init(struct iwl_trans *trans);
511int iwl_pcie_gen2_tx_init(struct iwl_trans *trans);
475void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
476int iwl_pcie_tx_stop(struct iwl_trans *trans);
477void iwl_pcie_tx_free(struct iwl_trans *trans);
478void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
479 const struct iwl_trans_txq_scd_cfg *cfg,
480 unsigned int wdg_timeout);
481void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
482 bool configure_scd);

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711}
712#endif
713
714int iwl_pci_fw_exit_d0i3(struct iwl_trans *trans);
715int iwl_pci_fw_enter_d0i3(struct iwl_trans *trans);
716
717void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable);
718
512void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr);
513int iwl_pcie_tx_stop(struct iwl_trans *trans);
514void iwl_pcie_tx_free(struct iwl_trans *trans);
515void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
516 const struct iwl_trans_txq_scd_cfg *cfg,
517 unsigned int wdg_timeout);
518void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
519 bool configure_scd);

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748}
749#endif
750
751int iwl_pci_fw_exit_d0i3(struct iwl_trans *trans);
752int iwl_pci_fw_enter_d0i3(struct iwl_trans *trans);
753
754void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable);
755
756/* common functions that are used by gen2 transport */
757void iwl_pcie_apm_config(struct iwl_trans *trans);
758int iwl_pcie_prepare_card_hw(struct iwl_trans *trans);
759void iwl_pcie_synchronize_irqs(struct iwl_trans *trans);
760bool iwl_trans_check_hw_rf_kill(struct iwl_trans *trans);
761
762/* transport gen 2 exported functions */
763int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
764 const struct fw_img *fw, bool run_in_rfkill);
765void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans, u32 scd_addr);
766
719#endif /* __iwl_trans_int_pcie_h__ */
767#endif /* __iwl_trans_int_pcie_h__ */